An Assembly Language for Reprogramming
Marvin Lowell Graham and Peter Zilahy Ingerman* Wesiinghouse Eledric Corporafion,^ Baltimore, Maryland
Complete reprogramming of compiler language programs is seldom necessary. It is assembly language programs which present the greatest difficulty. Assembly languages generally provide a one-for-one translation from a symbolic to a numeric version of a program, that is, from assembly language to machine language. The meta-language presented here can be used to specify the mapping of any language which conforms to a canonical list form into on arbitrary stream of bits. This bit stream may be treated as a machine language program, a character stream, or whatever else the user might desire. Thus, this meta-language can be used to map from one assembly language into another or from the assembly language for one machine into the machine language of another.
liilroduetion Halpern |1] has implemented an assembly meta-language wliich expects virtuallyevery line of a program to be either a macro call or a contribution to the definition of macro. Ill Haljiern's system, the ]iarameterization ^\ithin the macros is performed in terms of M'lnliolic (juahties. Ferguson [2], on the other hand, has implemented an assembly nicla-language in which the ]»arameterization within Ihe macros o|:ierates in terms of tlie execution time values of lhc symbols used in tlie macro call. This paper specifies an assembly meta-language based on the work of Ferguson, but in which the jiarameterization can at any ])oint be either by symbol or by ^'aIue. This system is currently being implemented at ilie AVestinghouse Defense and Space Center. The extension wliii'Ii is probably the most important in re|irogramming applications is the ability to inspect the lines preceding and following any line during the processing of that line. Consequently, translations from an assembly or machine language program for a multiple address machine is feasible, and vice versa. Disassembly is also possible, since the bit stream of the input machine language jirogram can be inspected and translation back to a suitable symbolic assembly language performed. It is imperative to recognize that the translation would necessarily be performed uniformly and Avithout bias on Ihe entire machine language bit stream, both the '•instructions" and the "data". The .symbolic re.sull of this translation will be nothing more than a reasonable facsim
Presented at the ACM Reproj^raniming Conference, Princeton, New Jersey, June 1965, co-sponsored by the Association for Computing Machinery tirid Ajiplied Datii Research, Inc. The uurk reporieil in this piiper has been sponsored in part by I lie Air Force Olfice of Scientific Hesoarch of the Office of Aerospace Uesearch, under Contract No. AF4(ii3S)1452. • Present address: RCA EDP Division, Cherry Hill, New Jersey. t Defense and Space Center.
ile of what the program would have looked like had the original programming been done in the language to which the translation was made. Since each word must be transhit cd as an instruction, tho.se words which are used entirely as data would none the less be translated into instructions.
1. Control Charaeters An assembly language program consists of a sequence of lines. Each line begins witli the control character "CR" anil extends to Ihe next such character. Each line consists of a sequence of lists, separated from each other by the control character "LS". "LS" is an infix operator so that the configuration "CR LS" imj^lie.s two lists, the first of which is null. Finally, each list consists of a sequence of items, separated from each other by the control character "IS", which is also an infix operator. Hence, the configuration "CR IS" implies that the first item of the first list is null. An example of a line is shown in Figiu'e 1. The control characters can be thought of as:
CR analogous to a carriage return im n ty|iewriter; IS analogous lo tin- (-(imina ot" SLEUTH II LS analogous tn the spare which must appear between SLEUTH 11 lists.
CR iltm IS Mem LS Hem IS .'em LS LS IS ilem 15 i ren.
LIST
VOID ITEM
VOID LIST
Fio. 1
It is significant to note that even though the control charactei's may have to be represented in some implementation as actual charactei-s, they must not be regarded or manipulated as objects in the input string, but merely as delimiters. Hence, the above analogies to the space and comma of SLEUTH II hold only where these characters serve as delimiters and not as objects.
2. Structure of a Line
The first two lists of a line have a tixed interpretation. The first list serves the function of the location identification in conventional assembly systems. The fii-st item of this list is generally construed to be a symbolic designation for the address of the line, and is called the label of the line. The second item of the list is taken to be the name (symbolic designation) of the location counter which is to control the allocation of the line (and all successive lines with a null location counter specification). The value of the third item of the list is the amount by which the location counter is to be incremented after processing the line. This item will often be null; in this case, the contents of the appro
/ Number 12 / Doccmher, l%.i Communications of the ACM •69
priate localion counter is modilied in a manner determined by the niiture of tho remainder of tlie line. The vahio of tlie fourth item specilied tho maximum depth in tho ]»rogt-am liw (sec 4.2), rehitive lo the current de|>th, at, which I he symbolic value and niuneric value of the label are to be ivailable fur jirocessing. Tho ^'alue of the fifth item specilies the depth in the prognun tree, relative to the current depth, al which tho symbol table entry is to be retained. The second list serves as an o|ieratoi* whose operands are the rest of Ihe lists on the line. The first, iiom of the second list identifies the oporation. Several primitives (basic o])eralions) are inherent to the assembler and function as defined below. Any other opei'atio!is must, be defined by the programmer as required, in terms of the primitives.
3. Additional Concepts
Items. The term item as used liere refers to a symbolic designation, a RADIX evocation (see 4.5), a FUNCTION evocation (see 4.(1.")) or any comhination of these elementary items with suitable arithmetic, Boolean, and/or relational operators including parentheses. The allowed operatoi-s (since they aro essentially conventional) are not enumerated here for the sake of brevity. The ends of an item are always delimited by control characters. Literals. Any item enclosed entirely in parentheses will be treated as a symbolic immediate address, sometimes called a literal, losing this technique, one may write on any line what he is referring to rather than where it is stored. The information enclosed \\'ithin the i)arentheses will be treated as a eompiete line with the left parenthesis serving as a pseudo "CR". The value of a numeric reference to a hteral is the value of the localion counter specified within the literal which was assigned \(> ihe first output line generated by the literal. A literal whose location counter specification is void will be allocated under control of the same location counter as the last previous literal. All literals under the control of the same location counter are pooled; that is, duplicates are eliminated. Line Counter. The character "S", when used as an elenieiitarj'- item, represents the value of the approj>riate location counter for the first output item generated for the current line. Hence, "S" will be regarded as a symbol which is inherently unredefinable by the programmer but continuously redehned by the system. If it appears on a line whose operator is a primitive, its value is determined by assuming that it occurred on the last previous nonprimitive hne. (In this context, the operator of a DO line is the operator the pseudo-hne included in it.) In addition, the value of the expression "S + n", for example, will be the value of the location counter which controls the allocation on the first out)>ut item generated by the «th following nonprimitive line when that item is generated. Hence, "S ± n" can be thought of as a present position relative address whose unit of measure is lines rather than locations.
Symbols. When any symbol occurs as item 1 of list 1 of a line whose operator is a nonprimitive, it takes the current value of the location counter controlling that line, and is entered in the symbol table with that value.
A symbol is subscripted \\Inn ii is inlldwi-.l by a list enclosed in parentheses. A snbscrijjti-d symbol S {il 18 /a... IS /„) has the a priori value equal to tho number of subscripted symbols S (ii IS 72... IS /„ IS /,,+i) for whii h I lie values of ij for 1 < j < n are identical. The a priori nuinorii; value nf the symbol "S" will be zero only when "S" followed by a sub.scrijjt list (either null or nonnull) appears somewhere in tho program. Otherwise "S" has a priori numeric value niill. The symbols at the end of the tree have either value zero (nof niilll) or flie value assigned by their having occurred in a (JENERATOK reference (see 4.6.2) or item 1 of list 1 of a line. All nonsubscripted symbols have an a priori null value.
4. Primitives
4.1 Line. This primitive defines the length of an output line. The format of a source line using this primitive is
CIt name LS LINE LS ii IS n IS I'a IS i*
The value of ii is the number of bits per output character under control of the LINE designation "name". The value of ^2 is the maximum number of such items in an output line. The value of i^ is the representation of the "null character" to be used in filhng fields which are not filled by the value of the item for fhe field. The value of i^ is limited to the values below and specified
0 Right justify the item values, 1 Left justify the item values.
4.2 Form. 71iis primitive defines the format of an output hne under the control of the LINE designation specified by "LINE-name". The format of a line using this primitive is
CR name LS FORM FS LINE-nnme LS /, IS 12 IS ... IS i, LS R
It is evoked by writing "name" as the operator of a line together with an o(3erand list with j items. When it is evoked, the values of tho j items are written as output, in the output file determined by the value of R, each with /„ (1 < n < j) charactei-s per item, justified and truncated in Ihe number of bits designated by the specified UNI*] definition. The outpni medium for each output file is installation dependent. Evocation of a FORM for which a null LINE-name specification was given will result in the use of LINE specification nsed for the list previously evoked FORM. The power and fiexibility of this type of assembly process is based on the fundamental concept that there is exactly one |irimitive whoso evocation causes output to be produced. Tho entire assembly process consists of a repeated evocation of a FORM definition with varying sets of parameters. A FORM can be evoked directly Ijy writing its label as tho operator of a line. However, a nesting process is available to the i)rogrammer (see 4.6) which allows him to evoke a complete subjirogram for assembly with one line. Nested evocations may be placed within nested
770 CommunicutionH <if the ACM Volimic » / Numlwr 12 / Dccvnil.ti.
•'Vocations ad iriritiilum. This nesting facility inipctses an iniplicit ii-ce sirnclin'o on each line of llie program. Each ^i^*' nt I III' Ill-sling process iricroascv lhc depth of the tree \>y nwr lr\rl. Tin- siilil H'cs Inr cadi line aro connected by \nluc (ll iheir liciiig in Ihc same program. Hence, the enIne luo^rani can lie regarded !is a free structure of |»aratiicterized evocations of I*"{)RM definitions.
4.:i J'JQU. This primitive causes item 1 of Iho list 1 lo III' placed in the symbol table wiih the value given in list 'A. The ('(iiinal cif a line usiii<; lhl^ primitive is
CK luiinr LS I'XJU LS item
If a symbol table entry has previously been made with "name" as its symbol, the new value will rei)lace the old one. If, however, the old value was unredefinable (that is. It occurred as item 1 of list 1 on a nonprimitive line), and the new value dif^'ers from the old one, a multiple definition indicafion will be given, no values will be changed, and no hnl her processing of fiie EQU line will bo done.
4.4 DO. This primitive in'ovides the means for repetili\e processing of given psendo-linc wliirh begins item 1 of list 4 of the DO hne. The value of item 1 of list 3 specifies tlie number of repetitions to be performed; a zero value c-anses tlie ])soudo-line to be disregarded. Item 2 of list 3 is the symbolic designation of the counter to be used for the duration of the repetition process; the confents of this counter can be accessed from fhe pseudoliiK' by this name. Its value begins at 1 and increases by 1 tnr eacli repetition of the pseudo-line. The repetition process stops when the counter contents becomes equal to the value of item 1 of list 3. The LS between lists 3 and 4 serves a.s a pseudo CK. The eontiguration "LS LS" implies a null first list for fhe pseudo-line. The format, of a line nsing fhis primitive is
CR name LS DO LS count IS cuunt.-r LS /, L8 /•• LS I3 . . .
4..3 RADIX. The forniaf ol a line using this primitive
is
CR name LS RADIX LS io IS (, IS ... IS ij-i
The /• items of list 3 are Iho symbols which will rejiresent flic digits of an integer with radix j; item ii, has value k. Tlie .symbol "name" must prefix the digit symbols; if "name" is the same as any of fhe if ems of list 3, it is to be regarded as a digit of the integer as well as a RADIX evocation.
•if^GENERATOR, ENTRY and FUNCTION 4.6.1. The primitives are more simply discussed to gether. The formats of lines nsing GENERATOR as a primitive are
CR namc'i LS GENIORATOR LS . . . CR nanii', LS ICN'TKV LS . . . CR name, LS ENTItY LS . . . CR LS END.
These lines define an oj)eratnr whose name is "namei". The GENERATOR is evoked by a line whose item 1, hst
2 IS one nf Iho iiaines of an I'iX'J'lO' line. The bf»fiy ol Ih'(il']i\'l']RATOR con.sistH of lines which evoke primitives and other GENERAT{iR8. Reference can be made within tho GENERATOR (o eifhor the numeric or symhwiic vahies of items on flM' evoking lino and its neighbors. Reference to a numorif: value is made by following fhe name f.f the GENERATOR, here "namei", with a list of items, called subscripts, enclosed in parenthesas. Reference to a symbolic value is made by following "namoi" wnth a list of itoms, called designators, enclosed in f)rackets. References to numeric values will be called numeric references; references to symbolic values will be called symbolic references. The following conventions hold.
4.t>.2. Generally, there are three items in ihe sub.script list. The value of item 1 designafes the line; line 0 is the evoking line, line 1 Ihe following, and line —1 the preceding, etc. The value of item 2 designafes tho list required on I he roforeiicod line. List 0 is list 3 of the relevant entry line of the GENERATOR for line 0, and is a null list for all other lines. The value of item 3 designates an item of the specified list. Any numeric reference wifh fewer than three subscripts takes tho a priori value normally assigned to a subscripted Iabol. Henee, the value of a numeric reference with fwo subscripts will be the number of items in the referenced list, since these items are all referenced with triply subscripted numeric references whose first two subscripts are identical to those of the doubly subscripted numeric reference. 4.6.3. Subscript 3 can take a special form which uses Iho control character "IJ", item juxtaposer. Its form is ihen
Ilcni A IJ it.-Mi B.
"IJ" is an infix operator. The value of item A designates an item of the S]iocified list. The value of item B designates which of several possible special questions is being asked about the designated ifem. The admissible item B values together wifh the information they request are
Vjlue Information Returned 0 Number of characters in the designated item. 1 One if the designated value references a defined RADIX; zero otherwise. 2 One if the designated item is redefinable; zero otherwise. 4.6.4. Generally, there are four items in the designator list. The value of item 1 designates the line with res])ect to the evoking line. The value of ifoni 2 de.signates the list on Ihe referenced line. The value of item 3 specifies an item of the referenced list. The value of item 4 designates a character of the referenced item. The value of a .symbolic reforonoe is determined by the number of designators it contains. The values are listed below.
A' umber of designators 1 2
3 4
Value Character string of evoking line. Character string of the designated list. Character string of the designated item. The designated character.
\,,liiinf fi / Number 12 / l>t-<:pniher, 1965 Comnniiiications of the ACM
•t,ti..i. The ulher ninlfi hne .slrnctiu't! is The general format of sovoral linos usinp; this primitive is
Cll nam.', LS KUNCTION LS . . . CR nanw; LS lONTHY LS . . . CR names LS KNTRY LS . . . CR LS END LS ilem
This sirvicture is evoked hy the occurrence of name2, naniOg, etc. in any item. Operands may bo presented to the FUNGTION l\y placing them iu lists in parenthesis after the name evocafion. The values of these operands aro rofercnced in tho body of the KUNGTION by subscripting namoi with the desired list and item number analogous to the reference to paranietei"s in tho body of a GENERATOR. The diffei-ence between the GENERATOR and FUNCTION primitives is that the former generally iiroduces output lines wiiereas the latter alwaysi:)roduoes a value for uso ill fiu'ther processing. The value returned by the FUNGTION is the value of "item" given on its END line evaluated with the values of its parameter at the time the END line is reached. 4.7 GO. This ])rimitive alters fhe sequence of inferprolation of the source lines. The format of a source line using the primitive is CR name LS GO LS label "Label" specifies the label of iho lines from wliich assembly is to jirooeed, subject to the following rostriction: Entry to a GENERATOR which was not being processed prior to ihe occurrence of the GO line must be made through an ENTRY line of the GENERATOR. 4.8 END. This jjrimitive has three distinct uses: (1) An END line must be given for each GENERATOR line. This nse of END signals the conclusion of fhe GENERATijR body. (2) An END line must bo given for each FUNGTION line. This use of END must have a nonvoid third list as described under FUNCTION, and signals the conclusion of the FUNCTION body. (3) An END line must ot cur as tho last line of every program. Hence, an END line must conclude every program and subprogram.
5. Conclusions The meta-language presented here can be used to specify the mapping of any language which conforms to the canonical list form into an arbitrary stream of bits. This output bit stream may be treated as a machine language program, a character stream, or whatever else the user might desire. For example, the input could be written in some arbitrary assembly language and the out)-iut be a machine language program for a particular machine. Convei-sely, the input might be written in a particular assembly language and the output bo a machine language jirogram for an arbitrary nmchino. (Of course, there is no way to provide for the case in which the programmer squares an instruction and executes the middle bits of the product, or any of the grueome analogs to this example.)
TIK^ pi'ohli^ni ol' 1'oprngi'a.niiiiint; lor nnc nia''liiiic the asseinbly-languago vorsions of programs wrilicn tm anollier can bo facilitated by the use of ihe techniques suggested by this paper. Given as input the juswenibly language (or the old inaiOiinc, either the machine code, the assembly laiigiiago or both, for tho new machine can bo generated. However, significant dillicnlf ios i-an arise when the source program includes serjuonces of code in which time delays are significant. This situation arises most frequently in sequences which perform input or output without library routines. These sequetices can bo traced at translation time using the GO primitive and the line scanning facility of the meta-language. Timing estimates can be constructed for all possibly critical sequences and diagnostic messages inserted where appropriafe. At worst, questionable sequences can be detected and indicated.
APPENDIX
Tho appendix presents ati example of the use of the language. The control characters used in tho example are:
CR LS IS
Beginning of the line Tab (sequence of spaces)
List one of all the examiile lines is intentionally incomplete for the sake of clarity; otherwise, the example is complete. Tho example shows how a UNIVAC 1107 {U1107) Block Transfer (BT) instruction could be mapped to IBM 7094 (17094) code assuming a particular mapping of tho registers of the UNIVAG 1107 to IBM 7094 oore memory. The 1107 block transfer instruction is executed in repeat mode. In the SLEUTH II language for the 1107, the block transfer instruction is written:
BT DESTINATION INDEX, ADDRESS, *SOURCE INDEX
The asterisk which precedes the source index specification indicates that the index registers are to be incremented for each transmission operation.
0. 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, (3, 7, S, 9 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 0, 1, 2, i, 4, 5, 6, 7, 8. 9 0. 1, 2,3, 4, 5,6, 7,8,9 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 0, 1, 2, 3, 4, 5, 6, 7. 8, 9 0, 1, 2, 3, 4, 5, 6, 7, 8, 0 0, 1,2,3,4,5,6,7,8,9 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 1. 3(1, 0, 0 W, 15, 3, 15 CODE
0, 053-iOO 0, 053500 CXI (0,0, 1), CXI (0,0, 2). CXI (0,3,2), CXI (0,3, 1)
772 CommunicationB of ihr
0 1 2 3 4 5 0 7 8 9 L I CXI LXA LAC
END CX2 PXD
RADIX RADIX RADIX RADIX RADIX RADIX RADIX RADIX RADIX RADIX LINE FORM, L GENERATOR ENTRY ENTRY I
GENERATOr; ENTRY
Voliinn
4. 075400
12 / December, I9(i5
ni\ KNTllY
END CT ri.A CLA' STO
END CX3 TIX
G BT Gl INC
I
CM-JNERATOR I':N"I"I.'V r:.\'ri;>' ICNTKV 1
GENERATOR KNTin" I
GIJ:NERATOR ENTRY GENERATOR ENTRV PXI) SUB PDX PXD SUB PDX END FLAG
CX2 (0, 0, (0,3, 1),
11, ll'tOdlHI
(1. 0511011(1
II. OlHHnO
1), CX'J (1
CT (U, U, 1), CT (0, (0,3,2),
CX3 (0, 0, (0,3,2),
13
G (0, 3
G 7 G (0, 3, 3) 7
EOU G
CT (0, 3
1), CX3 CX3 (0,
, 1)
[0. 3. 3. 1
(0, 0, 2), CX2
O,'J),CT , 1)
(0,3,3), CX3 3,1)
1 = 1*1
A
DO LXA LAC LAC! CLA STO DO
TIX END
FLA(j G 10,;;,:., i lie, 5 G (0,3, U,(i G (0,3, 3), 7 G (0, 3, 2), 7 G (0, 3, 2,) 0 FLAG LS LS INC separators here) A, 5, 1
REFERENCES
KQU
(note; 2 list
1. HALPERN, M. I. XPOP; A metalanguage withont metaphysics. Proc. 1964 Eall Joint Comput. Crnif., Vol. 26, Spartan Books, Washington, D.C, 1904. 2. FiiRGUsoN, D. E. A meta-assembly language. Programmatica, Los Angeles, 3. INGERMAN, P. Z. The parameterization of the translation process. Paper presented at IFIP Working Conference on Formal Language .Specification Languages, Baden, Austria, Sept. 19(j4. 4. Reference Manual IBM 7ttJ4 Data Processing System, Form A22-6703, IBM, Customer Manuals, Department 298, P.O. Box 390, Poughkeepsie, N.Y. 5. Central Computer Manual, UP-24tJ3 Rev, 2, Systems Programming Library Services, UNIVAC Engineering Center, Plant 2 Box 999, Bluebell, Pa,
1401 Compatibility Feature on the IBM System/360 Model 30
M. A. McCormack, T. T. Schansman and K. K. Womack
/BM Corporofion,* Endicott, New York
The "second generation" of stored-program computers, of which the IBM 1400 series wos a part, brought EDP into the mass market for the first time on a large scale. As this era unfolded, rapid changes in technology led to rapid obsolescence of data processing equipment. Programs written for a particulor system required tedious conversion as incompatible new machines came into use. The IBM System 360 has been designed with the conversion problem specificolly in mind. One of the conversion aids available on the Model 30 is the 1401 compatibility feature. This feature, in conjunction with other aids, permits a smooth and inexpensive transition to optimum use of the new system.
Introduction III the past it has not geiu'ially been economically feasible to implement two (iissimilar machine languages within a single processor. Today, the Read Only Storage Controls used in IBM System/360 make it economically feasible to implement the languages of current systems within System/360. To give as complete a picture of this new implementation technique as possible, remarks will be restricted to implementation of the MOl <(impatibility feature on Systein/360 Model 30.
The ] JOl Compatibility Feature Two principal convereion methods have evolved from second generation techiutlogj': program translation and simulation. In considering a meUujti of conversion for 1400 series programs to the Model 30, both of these eonvei-sion methods were considered, but were rejected as being either too slow or requiring too much manual intervention. The objective was to pro^^ide a means of running 1400 series programs on the Model 30 without change. The introduction of the 1401 compatibility feature on the IBM 1410 had shown historically that such an objective could be achieved in a machine of similar internal organization. Ease of use and sjieed were demonstrated to be the primary advantages of having a compatibility feature. In the past, it was considered impossible to implement two completely different machine organizations in one processor, without incuriing exceptional costs and intolerable inefficiency. However, in the ease of the Model 30, it seemed that Read Only Storage Controls make manipu
Presented at the .^CM Ueprngramming Conference, Princeton, N. J,, June 19G5, co-sponsorod by the Association fur Computing Machinery and Applied Data Research, Inc. * Systems Developnieiit nivisinn.
Volume 8 / Niiinhcr 12 / 1965 of
Sweet Ortiz
Rabu, 19 April 2017
Selasa, 28 Maret 2017
An 8-Bit, 40-Instructions-Per-Second Organic
Microprocessor on Plastic Foil
Kris Myny, Student Member, IEEE,
Erik van Veenendaal, Gerwin H. Gelinck, Jan Genoe, Member, IEEE,
Wim Dehaene, Senior Member, IEEE, and Paul Heremans
Abstract—Forty years after the first silicon microprocessors,
we Plastic electronics refers to the technology to make transistors demonstrate an 8-bit microprocessor made from plastic
electronic and circuits with thin-film organic or plastic
semiconductors technology directly ontion is
as low as 100today limited to 40 instructions per second. The pW. The ALU-foil
operates at a supply voltageflexible plastic foil. The operation speed isower
consump- on arbitrary substrates, including not only rigas glass,
but also flexible plastic foils. A variid substrates suchety of organic of 10 V and back-gate voltage of 50 V. The
microprocessor can molecules and polymers have been developed as
semiconducexecute user-defined programs: we
demonstrate the execution of tors, and the best ones [1]–[4] today
feature a charge carrier
the multiplication of two 4-bit numbers and the calculation of themoving
average of a string of incoming 6-bit numbers. To executesuch dedicated tasks
on the microprocessor, we create small plastic mobility on the order
of 1–10 cmlower than that of silicon. When integrated/Vs, some 100into
circuits, theto 1000 times circuits
that generate the sequences of appropriate instructions. realistic
mobility values are somewhat lower but nevertheless The near transparency, mechanical flexibility, and low power con- sufficient
for applications such as backplanes for flexible sumption of the processor are attractive features for integration on active-matrix
displays, in particular for flexible electronic everyday objects, where it could be programmed as, amongst
otheritems, a
calculator, timer, or game controller. papers [5]. The first
dedicated circuit applications of organic thin-film transistors have also
appeared in recent years, such cessor,organic
processor, organic transiIndex Terms—flexible
processor, organic circuits, organic microprocessor,Dual-gate, flexible
circuits,stor, plastic circuits, plasticflexible micropro- as
recently demonstrated by the idriver for an organic active matrix OLED display
[6]. Such cir-ntegration of an organic line microprocessor, plastic processor. cuits can be made directly
on thin and ultra-flexible plastic foils, which allows them to be very simply
laminated on everyday objects, and furthermore provides appealing
characteristics in
I.
INTRODUCTION terms
of bending radius and robustness: we no longer talk of
E
|
LECTRONICS pervades everyday life and is undeniably flexible
electronics but of truly crinkable electronics [7].
making its way from computing to
telephony and to as- Here, we investigate the possibility to use this
technology to sisting us in everyday tasks through products such as electronic
realize microprocessors on plastic foil. As the cost of an elecpaper to read
and write, electronic noses to sense gases, smart tronic chip decreases with
production volume, ultralow-cost milighting with electronics to save energy,
and so on. The key en- croprocessors on easy-to-integrate flexible foils will
be an enabler of these pervasive electronics applications is the fact that
abler for ambient intelligence: one and the same type of chip integration of
ever more transistors with ever smaller dimen- can be integrated on vastly
different types of objects to perform sions has resulted in the cost of a
single semiconductor tran- customized functions, such as identification, simple
computing, sistor, or switch, to dwindle to the level of ten nano-dollars per
and controlling.
transistor. Nevertheless, if the cost of a
transistor in a chip is The organic microprocessor has been implemented as two
negligible and decreasing, the cost of placing and routing elec- different
foils: an arithmetic and logic unit (ALU) foil and an tronics on daily objects
is not necessarily proportionally low. instruction foil. The ALU-foil is a
general-purpose foil which can execute a multitude of functions. On the other
hand, the in-
Manuscript received May 07, 2011; revised July 17, 2011;
accepted struction foil is a dedicated chip that generates the sequence
of September 05, 2011. Date of publication November 04, 2011; date of
current instructions to obtain a specific function. It sends this
sequence version December 23, 2011. This paper was approved by Guest Editor
Satoshi of instructions to the ALU-foil such that the combination of
both
Shigematsu. This work was supported in part by the EU-Projects COSMIC(ISTIP-247681) and ORICLA (FP7-ICT-2009-4 247798). foils results in the execution of a specific algorithm. The first
K. Myny is
with imec, 3001 Leuven, Belgium, the Katholieke Universiteit prototype
of the organic microprocessor [8] had only one inLeuven, 3001 Leuven, Belgium, and
also with the Katholieke Hogeschool Lim- struction foil available and
could operate up to six operations burg, 3590 Diepenbeek, Belgium (e-mail:
kris.myny@imec.be).E. van Veenendaal is with Polymer Vision, 5656 AE Eindhoven,
The Nether- per second (OPS). In this paper, we report an improved
organic lands. microprocessor that can run 40 OPS and can operate with two
J. Genoe is with imec, 3001 Leuven,
Belgium, and also with the Katholieke different
instruction foils. We first discuss the technology and
Hogeschool Limburg, 3590
Diepenbeek, Belgium.G. H. Gelinck is with the Holst Centre/TNO, 5605 KN
Eindhoven, The choice of logic
family used for the microprocessor foil. Sub-
Netherlands. sequently,
we report on the design and measurement data of
W. Dehaene,
and P. Heremans are with imec, 3001 Leuven, Belgium, and the ALU-foil.
Next, a complete integrated microprocessor is also with the Katholieke
Universiteit Leuven, 3001 Leuven, Belgium.Color versions of one or more of the figures
in this paper are available online demonstrated by combining the
ALU-foil with the instruction at http://ieeexplore.ieee.org. foil. Finally,
we conclude by comparing the organic micropro-
Digital Object Identifier 10.1109/JSSC.2011.2170635 cessor
to the silicon Intel 4004 early-days processor.
0018-9200/$26.00 © 2011 IEEE
back-gate as -control gate (right). (Figures from [11].)
II. TECHNOLOGY AND LOGIC FAMILY
In our organic thin-film transistor (OTFT) technology, all
layers to make the circuits are processed directly on a 25-m-thick PEN
(polyethylene naphthalate) foil and consist of polymers or organic molecules,
with the exception of metals (Au) for gates, sources, drains, and interconnect
lines between the transistors [9]. The OTFT technology is a unipolar p-type,
single- technology, using pentacene as semiconductor.
The basic transistor has a channel length of 5 m.
The yield of larger integrated circuits in such a single-, p-type-only
technology is intrinsically limited, as a result of the parameter variability
[10]. Myny et al. have demonstrated
an increased circuitrobustnessby the additionofan extra gate to each OTFT,
leading to the availability of multiple ’s in a
unipolar p-type technology [11]. The organic microprocessor has been designed
in this technology. A cross section is shown in Fig. 1. As depicted, each TFT
comprises two gates, a front gate and a back gate. The front gate controls the
channel current while the back gate, which is weakly coupled to the
semiconductor channel, is used to shift the transistor’s threshold voltage.
This is depicted in Fig. 1. As a consequence, the of each single transistor can be independently
tuned.
The
key factor when determining the choice of logic family for the basic circuit
gates is the circuit robustness parameterized by the noise margin. Fig. 2 shows
the noise margin (at 20 V) of
typical zero- inverters when no back-gate is used, compared with the noise
margin achievable with an optimized dual-gate zero- topology. In this optimized
topology, the back gatesoftheload transistorsareconnectedtothefrontgates, while
all back gates of the drive transistors are connected to a common rail, to
which a back-gate voltage is applied externally [11].
The typical spread on threshold voltage in organic TFT
technology is 0.2 to 0.5 V, which is large compared with the noise margin
achievable with single-gate technology. As a result, it is common practice in
the field of organic electronics to use a transistor-level approach to design
(simple) circuits. Indeed, it is usually necessary to simulate the schematic
entry with an analog circuit-level simulator (such as Spectre or Spice) and use
Monte Carlo simulations to predict yield.
However, such analog circuit-level simulators are not adapted to deal with the
needed level of complexity to design and simulate an organic microprocessor due
to the large number of (parallel) switching gates, large amount of input,
control, and output signals. In contrast, in our optimized dual-gate, the much
improved noise margin allows to make use of common digital design practices.
Starting from the basic characteristics of inverters and other logic gates, we designed
a robust library of basic digital logic gates (inverters, NANDs,
buffers). This standard cell library was used to
design
the organic microprocessor by means of a gate-level design approach. Therefore,
after modeling, simulating, and measuring the basic building blocks, we used a
gate-level simulator (Modelsim) with our standard cell library to design and
simulate the organic microprocessor. The ratio between drive and load
transistor for the logic gates in the library was a 1:1 ratio beneficial for
area, with a minimal of 140/5 m/ m.
Figs. 3 and 11 show photographs of some microprocessors on
foil. The 25-m-thick foil
is highly flexible. Furthermore, the complete circuit is nearly transparent, as
only the metal electrodes of gates, sources, drains and interconnect lines are
reflective.
III. ARCHITECTURE
AND MEASUREMENT RESULTS OF THE
ORGANIC ALU-FOIL
Characteristic to a microprocessor is that its hardware is
not dedicated to a single function or operation, but is designed such that the
operations performed on (digital) inputs can be programmed and defined after
manufacture of the processor. The challenge, therefore, is to manage the
plurality of possible critical data paths in the microprocessor, for all
different instruction codes and inevitable variations due to nature of organic
technology on foil. Our microprocessor has been constructed around an 8-bit
arithmetic and logic unit (ALU) which comprises three blocks as schematically
represented in Fig. 4. The first block adds or subtracts the incoming numbers
(arithmetic unit), the second block performs logic operations on the incoming
data (logic unit) and the third block shifts the incoming bits (bit shift
unit). The arithmetic unit is designed as a ripple carry adder/subtractor.
Detailed control over each of these three blocks and the actual selection of
the output of the ALU unit is determined by the microprocessor’s instruction
set, also called
Fig. 4. Symbol (top-left),
instruction set (bottom-left), and architecture (right) of the main building
block of the microprocessor, namely the 8-bit ALU. Three operational code bits,
opcode(2:0), are used to select among the different instructions.
operational codes or “opcodes” (Fig. 4). As
the architecture depicts, the ALU executes every clock cycle instructions on
each of the three units in parallel. Subsequently, a multiplexer selects the
desired instruction to be executed in that clock cycle.
Fig. 5 outlines the complete architecture of the
microprocessor foil. Around this ALU, a minimal set of 8-bit registers has been
placed, for storing the working data (accumulator A, working registers (C0, C1
and C2) and an output register). The storing and loading of the data in these
registers is also controlled by the instruction set. The registers select bits
(RR in the table of Fig. 5) correspond to bits 7 and 8 of the opcode and are
used to select between the four working registers, C0 to C3. Working register
C3 is implemented as a hard-coded decimal 1 in order to ease the implementation
of the increment and decrement instructions.
Fig. 5. (A) Architecture of the microprocessor core,
comprising the Arithmetic and Logical Unit (ALU), accumulator register “A”
and output register “OUT” at the top
and the input multiplexer and storage registers “C” at the bottom. (B)
Implemented instruction set: RR refers to the binary representation of the
selected
|
We
have tested all of the individual instructions of the microprocessor foil
extensively for different bias conditions. Fig. 6(A) shows that the
microprocessor can operate at up to 40 OPS, when powered at a 20-V supply
voltage and an appropriate back-gate voltage. This maximum frequency is
determined by the 25-ms critical path delay in the design. Fig. 6(B) shows that
the microprocessor can operate at voltages down to 10 V. The critical path is
defined by the subtract operation, where the carry bits need to ripple
subsequently through each of the bits. As shown in Fig. 7, the contribution of
these logic gates was measured separately on different kinds of ring
oscillators, as a function of the capacitive load of the gates. An inverter
driving a single subsequent stage has a minimum capacitive load, and in that
case its gate delay is 83 s. Similarly, the minimum gate delay of a two-input NAND is
126 s, while one input is connected to . However,
when a logic gate has to drive multiple subsequent stages in parallel, it is
slowed down: we show in Fig. 7 that a gate driving nine identical inverter
gates in parallel is slowed down to 1 ms. This gate delay, combined with the
length of the critical path, explains why with our current design and topology,
the processor frequency is 40 OPS. Moreover, because it was the first time a
circuit of this complexity was realized in organic technology, we preferred
conservative design choices. For instance, we utilized only gates with a fan-in
of 2 and our signal buffering strategy was very conservative. By alleviating
these restrictions and by optimizing the design, we estimate that the frequency
can improve towards the hundreds of OPS range. Another reason for the current
limitation to the tens of OPS range is related to the choice of logic family,
where we have chosen for robustness. Other unipolar logic types (dual-gate,
diode-connected) are more advantageous in terms of speed [11]. As Figs. 6(A)
and 7 also depict, the frequency of the ALU and the ring oscillator decreases
when the back-gate voltage
gate delay of the individual
inverters of the chain. The stage delay of inverters driving five and nine
gates have corresponding labels. The triangles show the measured stage delay of
two-input NAND gates driving one, five, and nine subsequent gates.
of the drive transistors increases. This
can be explained by a negative -shift of the
drive TFT yielding less drive current
[11].
Fig. 8. Demonstration of user-programmability of the
microprocessor. (A) Time evolution of the 4-bit input signals and the 8-bit
output signal when the multiplier instruction set (see Fig. 9) is implemented
in the organic microprocessor foil. The top axis shows the cycle number of
the program loop. (B) The 6-bit input signal (left axis) and the 7-bit output
signal (right axis, which has one significant binary digit more than the
input) when the running averager program (see Fig. 10) is executed. The top
axis shows the cycle number of the program loop.
Fig. 9.
Architecture and operation of instruction sequence generating circuits on
foil. (A) Schematic of instruction generating foils: n is 5 in case of the
multiplier foil and 4 for the running averager. (B) Program listing of the
dedicated instruction set of the multiplier, the execution of which can be
followed by the example shown in (C): the instruction lines of the code (B)
have been colored using the same color code as the outcome that they produce
in the multiplication of 1010 (10)
|
and 0111 (7) in (C). (D) shows the program instruction for the moving averager.
Furthermore, we show that our microprocessor is truly a
general-purpose machine that can be programmed for multiple uses by executing
instruction codes for different applications. To this end, a test board was
developed that programs the microprocessor. In a first example, shown in Fig.
8(A), the microprocessor is programmed to execute a multiplication of two
numbers. The solid line shows a sequence of cycles, in each of which two 4-bit
numbers are multiplied to give an 8-bit output value, shown as dotted line. The
input values are shown on the left scale (from 0 to 15), while the output is
shown on the right scale (0 to 255). The first cycle shows the multiplication
of the binary numbers 0111 (decimal 7) and 1010 (decimal 10) to 01000110
(decimal 70). This value remains at the output while two new numbers are fed in
at the input (0000 and 1111) and multiplied. In the third cycle, the output of
this multiplication (00000000) appears at the output while a new set is
provided and executed, and so on. The processor clock can be verified to run at
40 Hz during this execution, as explained above.
Fig. 10. Demonstration of
operation of the plastic microprocessor commanded by an instruction foil. (A)
Decimal representation of the measured seven least significant bits of the
instruction generated by the running averager instruction foil running at 70
Hz. The clock is shown at the right-hand axis. The data is valid on the rising
edge of the clock. (B) Measured output of the microprocessor foil connected to
the running averager instruction foil. As the input bit stream switches from
000000 to 000111, the output gradually increases to the same level over three
loop cycles, but with seven significant binary digits.
In a different example, chosen from the application domain
of digital signal processing, the microprocessor executes the weighed
time-averaging of a stream of incoming digital inputs to reduce random noise.
This algorithm is known to clean up the output signal of a sensor after
digitization by an analog-to-digital converter (ADC). By virtue of its
applicability to large area
Fig. 11. Photograph of the 8-bit ALU-foil.
substrates, plastic electronics is suited
to develop large-area sensors [12], and the first plastic ADC converters were
shown recently [13], [14]. We implemented the algorithm of a moving averager,
i.e., an averaging algorithm in which the weight of the past data decreases
exponentially, and demonstrate the execution of the algorithm in Fig. 8(B). The
6-bit input provided to the microprocessor is shown as the red line: 001111
(15) during the first four loop cycles, then 111101 (61) during the next 10
cycles, then 000110 (6). The running averager calculates the weighed average as
a 7-bit number, which can be seen to tend to the steady input values after they
have been provided for some cycles. Here again, the clock speed of the
processor is 40 Hz.
IV. INTEGRATED ORGANIC MICROPROCESSOR ON FOIL
Until now, only the ALU-foil of the microprocessor core was
discussed. In the above demonstrations, the instructions for the microprocessor
were generated by external test equipment. To come to a complete plastic
solution, we also designed a plastic control unit, shown Fig. 9(A). This
control unit has as task to take instructions from a memory in the appropriate
order controlled by a program counter. These instructions are sent as opcodes
to the microprocessor core. Opcodes for the program counter are also generated
to enable branching in the program. In the ideal case, the program would be
stored in programmable, nonvolatile memory on the foil. However, programmable
nonvolatile memory compatible with plastic thin-film transistors on foil is
still subject of research today and is as such not available for our
experiments. Therefore, like in the early days of silicon technology, we used
true read-only memory (ROM): the
TABLE I
SPECIFICATIONS OF THE CIRCUIT FOILS
TABLE II COMPARISON WITH THE EARLY SILICON PROCESSOR
instructions are hardcoded on the foil. A
different foil is designed for every program. For the low-cost, low-complexity
but high-volume applications that are envisaged here, this procedure could even
be a realistic commercial scenario. The instruction sets generated by the
multiplier instruction foil and the moving averager foil are shown in Fig. 9(B)
and (D), respectively.
The operation of the running averager instruction foil by
itself is shown in Fig. 10(A). This circuit does not contain a ripple carry adder,
and therefore it has a shorter critical path compared with the microprocessor.
Stand-alone, the instruction circuit can run at a clock speed of 70 Hz.
Finally,wedemonstrate thecombined operation of
aninstruction foil with the microprocessor. We conducted this experiment with
the running averager. The correct operation of this combination is shown in
Fig. 10(B). This demonstration shows that the microprocessor can indeed accept
its instruction set from a dedicated plastic circuit and is not limited to
instruction sets from a test board.
V. CONCLUSION
In Table I, we summarize the circuits fabricated and
demonstrated in plastic technology. With less than 100 W, the power
consumption of the flexible chips is already quite low and could further be
reduced by voltage scaling in the future [15], [16]. Such very low power
consumption is very important for widespread mobile applications on everyday
objects.
To conclude, we compare in Table II the characteristics of
the first plastic microprocessor with the early silicon processors made in
p-type-only silicon technology some four decades ago.[1] Significant
correspondence can be seen regarding parameters such as gate length, supply
voltage and transistor count, but some marked differences are also clear. The
instruction rate of the plastic technology is about three orders of magnitude
slower than the early silicon processor, as a direct consequence of the
three-orders-of-magnitude lower carrier mobility in organic semiconductors.
However, on the positive side, the power consumption is also four orders of
magnitude smaller. In future implementations, semiconductors such as amorphous
oxides [17] could boost the performance to an intermediate speed, with still
very attractive power consumption for low-cost, lowperformance, and mobile
applications.
ACKNOWLEDGMENT
This work was performed in a collaboration between imec and
TNO in the frame of the HOLST Centre.
REFERENCES
[1] P. T. Herwig
and K. Müllen, “A soluble pentacene precursor: Synthesis, solid-state
conversion into pentacene and application in a fieldeffect transistor,” Adv. Mater., vol. 11, pp. 480–483, 1999.
[2] J. H. Chen,
S. Subramaniam, S. R. Parkin, M. Siegler, K. Gallup, C. Haughn, D. C. Martin,
and J. E. Anthony, “The influence of side chains on the structures and
properties of functionalized pentacenes,” J.
Mater. Chemistry, vol. 18, no. 17, p. 1961, 2008.
[3] N.
Kobayashi, M. Sasaki, and K. Nomoto, “Stable peri-Xanthenoxanthene thin-film
transistors with efficient carrier injection,” Chemistry Mater., vol. 21, no. 3, p. 552, 2009.
[4] B. Yoo, B.
A. Jones, D. Basu, D. Fine, T. Jung, S. Mohapatra, A. Facchetti, K. Dimmler, M.
R. Wasielewski, T. J. Marks, and A. Dodabalapur, “High-performance
solution-deposited n-channel organic transistors and their complementary
circuits,” Adv. Mater., vol. 19, no.
22, p. 4028, 2007.
[5] G. H.
Gelinck, H. E. A. Huitema, E. van Veenendaal, E. Cantatore, L. Schrijnemakers,
J. B. P. H. van der Putten, T. C. T. Geuns, M. Beenhakkers, B. Giesbers, B.-H.
Huisman, E. M. Benito, F. J. Touwslager, A. Marsman, B. van Rens, and D. M. de
Leeuw, “Flexible active matrix displays and shift registers based on
solution-processed organic transistors,” Nature
Mater., vol. 3, p. 106, 2004.
[6] M. Noda, N.
Kobayashi, M. Katsuhara, A. Yumoto, S. Ushikura, R. Yasuda, N. Hirai, G.
Yukawa, I. Yagi, and K. Nomoto, “A rollable AM-OLED display driven by OTFTs,”
in Proc. SID, 2010, vol. 41, no. 1,
pp. 710–713.
[7] J. A.
Rogers, T. Someya, and Y. Huang, “Materials and mechanics for stretchable
electronics,” Science, vol. 327, p.
1603, 2010.
[8] K. Myny, E.
van Veendendaal, G. H. Gelinck, J. Genoe, W. Dehaene, and P. Heremans, “An 8b
organic microprocessor on plastic foil,” in Proc.
ISSCC, San Francisco, CA, Feb. 20–24, 2011, Session 18.1.
[9] H. E. A.
Huitema, “Rollable displays: The start of a new mobile device generation,” in Proc. 7th Annu. USDC Flexible Electron.
Displays Conf., Phoenix, AZ, Jan. 2008.
[10] S. De
Vusser, J. Genoe, and P. Heremans, “Influence of transistor parameters on the
noise margin of organic digital circuits,” IEEE
Trans. Electron Devices, vol. 53, no. 4, pp. 601–610, Apr. 2006.
[11] K. Myny, M.
J. Beenhakkers, N. A. J. M. van Aerle, G. H. Gelinck, J. Genoe, W. Dehaene, and
P. Heremans, “Unipolar organic transistor circuits made robust by dual-gate
technology,” IEEE J. Solid-State Circuits,
vol. 46, no. 5, pp. 1223–1230, May 2011.
[12] T. Someya,
T. Sekitani, S. Iba, Y. Kato, H. Kawaguchi, and T. Sakurai, “A large-area, flexible
pressure sensor matrix with organic field-effect transistors for artificial
skin applications,” in Proc. Nat. Acad.
Sci., 2004, vol. 101, p. 9966.
[13] H. Marien,
M. S. J. Steyaert, E. van Veenendaal, and P. Heremans, “A fully integrated
delta sigma ADC in organic thin-film transistor technology on flexible plastic
foil,” IEEE J. Solid-State Circuits,
vol. 46, no. 2, pp. 276–284, Feb, 2011.
[14] W. Xiong, Y.
Guo, U. Zschieschang, H. Klauk, and B. Murmann, “A 3-V, 6-bit C-2C
digital-to-analog converter using complementary organic thin-film transistors
on glass,” IEEE J. Solid-State Circuits,
vol. 45, no. 7, pp. 1380–1388, Jul. 2010.
[15]
H. Klauk, U. Zschieschang, J. Pflaum, and M. Halik,
“Ultralow-power organic complementary circuits,” Nature, vol. 445, p. 745, 2007.
[16] S. A.
DiBenedetto, D. Frattarelli, M. A. Ratner, A. Facchetti, and T. J. Marks,
“Vapor phase self-assembly of molecular gate dielectrics for thin film
transistors,” J. Amer. Chem. Soc.,
vol. 130, no. 24, p. 7528, 2008.
[17] K. Nomura,
H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature
fabrication of transparent flexible thin-film transistors using amorphous oxide
semiconductors,” Nature, vol. 432,
pp. 488–492, 2004.
Kris Myny (S’08) was born in Hasselt,
Belgium, on July 26, 1980. He received the M.S. degree from the Katholieke
Hogeschool Limburg, Diepenbeek, Belgium in, 2002. He is currently working
toward the Ph.D. degree on the design of organic circuits at Katholieke Universiteit
Leuven, Leuven, Belgium. He joined imec, Leuven, Belegium, in 2004 as a Member
of the Polymer and Molecular Electronics group. His main research interests are
the design, fabrication and optimization of digital organic circuits for
amongst others organic RFID tags and AMOLED-backplanes.
Mr. Myny was the recipient of the imec 2010 Scientific
Excellence Award.
Erik van Veenendaal received the Ph.D. degree in
physical chemistry from the University of Nijmegen, Nijmegen, The Netherlands,
in 2001.
In the same
year, he joined Philips Research Eindhoven, Eindhoven, The Netherlands,to work
on characterization and modeling of organic electronics. In 2003, with the
launch of Polymer Vision as an internal Philips company, his work focused on
the characterization of organic electronics enabled displays and setting up the
quality and reliability program for rollable displays. Currently, his main
responsibilities
as principal scientist at
Polymer Vision BV, Eindhoven, include R&D into future generations of rollable
displays and management of subsidy R&D programs.
Gerwin H. Gelinck received the Ph.D. degree
from the Technical University of Delft, Delft, The Netherlands, in 1998.
That same
year, he joined Philips Research as a Senior Scientist, where he began working
on polymer and organic transistors and their use in integrated circuits,
displays and memories. In 2002 he was co-founder of Polymer Vision BV,
Eindhoven, The Netherlands. From 2002 to 2006, he was Chief Scientist of
Polymer Vision. Since 2007 he is
Program Manager of “Organic
and Oxide Circuitry”
at the Holst Centre, which is
a joint research initiative of TNO and imec.
Jan Genoe (S’87–M’02) was born in Leuven,
Belgium, on May 19, 1965. He received the M.S. degree in electrical engineering
and Ph.D. degree from the Katholieke Universiteit Leuven, in 1988 and 1994,
respectively.
Afterward,
he joined the Grenoble High Magnetic Field Laboratory as a Human Capital and
Mobility Fellow of the European Community. In 1997, he became a Lecturer with
the Katholieke Hogeschool Limburg (KHLim), Diepenbeek, Belgium. Since
2003, he has been both
Professor with KHLim and
head of the Polymer and
Molecular Electronics (PME) group of imec. His current research interests are
organic and oxide transistors and circuits as well as organic photovoltaics. He
is the author and coauthor of approximately 90 papers in refereed journals.
Wim Dehaene (S’89–M’97–SM’04) was born in
Nijmegen, The Netherlands, in 1967. He received the M.Sc. degree in electrical
and mechanical engineering and Ph.D. degree from the Katholieke Universiteit
Leuven, Leuven, Belgium, in 1991 and 1996, respectively. His dissertation is
entitled “CMOS integrated circuits for analog signal processing in hard disk
systems.”
After
receiving the M.Sc. degree, he was a Research Assistant with the ESAT-MICAS
Laboratory of the Katholieke Universiteit Leuven. His research
involved the design of novel
CMOS building blocks for hard disk systems. The research was first sponsored by
the IWONL (Belgian Institute for Science and Research in Industry and
agriculture) and later by the IWT (the Flemish institute for Scientific
Research in the Industry). In November 1996, he joined Alcatel
Microelectronics, Belgium. There he was a Senior Project Leader for the
feasibility, design, and development of mixed-mode systems-on-chip. The
application domains were telephony, xDSL and high speed wireless LAN. In July
2002, he joined the staff of the ESAT-MICAS laboratory of the Katholieke
Universiteit Leuven, where he is now a Full Professor. His research domain is
circuit level design of digital circuits. The current focus is on ultra low
power signal processing and memories in advanced CMOS technologies. Part of
this research is performed in cooperation with imec, Leuven, Belgium, where he
is also a part-time Principal Scientist. He is currently teaching several
classes on electrical engineering and digital circuit and system design.
Paul Heremans received the Ph.D. degree in
electrical engineering from the University of Leuven, Leuven, Belgium, in 1990,
on hot-carrier degradation of MOS transistors.
He then
joined the Opto-electronics Group of imec, Leuven, Belgium, where he worked on
optical interchip interconnects, and on high-efficiency III-V thin-film
surface-textured light-emitting diodes. His current research interest is oxide
and organic electronics, including circuits, backplanes and memories, as well
as organic photovoltaics. He is an imec Fellow, Director of imec’s Large Area
Electronics department and part-time Professor at the Electrical Engineering
Department of the University of Leuven and editor of Organic Electronics.
[1]
Historic data are collected on the Intel Museum. [Online]. Available:
http://www.intel.com/about/companyinfo/museum/exhibits/4004/index.htm. The
specifications can be found at http://datasheets.chipdb.org/Intel/MCS-4/
datashts/intel-4004.pdf
Cooling of microprocessors
with micro-evaporation: A novel two-phase cooling cycle
Jackson Braz Marcinichen a,*, John Richard Thome a, Bruno Michel b
aLaboratory
of Heat and Mass Transfer (LTCM), Faculty of Engineering (STI), E´cole
Polytechnique Fe´de´rale de Lausanne (EPFL), Station 9, CH-1015 Lausanne,
Switzerland
b IBM
Research GmbH, Zurich Research Laboratory, Sa¨umerstrasse 4, CH-8803
Ru¨schlikon, Switzerland Dedicated to Professor Dr.-Ing. Dr.h.c.mult. Karl
Stephan on the occasion of his 80th birthday.
a r t i c l e i n f o a b s t r a c t
Article
history:
Received 4 March 2010
Received in revised form 3 June 2010
Accepted 5 June 2010 Available online 12 June 2010
Keywords:
Cooling
Component
Electronic
Microprocessor-design
Comparison
Cooling circuit
COP
Heat recovery
|
Three micro-evaporator cooling cycles, one with a pump, one
with a compressor and a hybrid of the two together, are proposed for cooling
a computer blade server. The hybrid cycle is characterized by the
interchangeability between the first two cycles, where the decision on the
cycle to operate is based on the season (necessity or economical benefit for
heat recovery) or the maintenance of cycle’s driver. The main characteristics
of each cycle are presented as well as the details of the micro-evaporator cooler
for the blade’s CPU. Analysis of the cycle overall efficiency and the
potential for heat recovery shows that the best cycle to use depends mainly
on the end application of the heat recovered. Four refrigerants were
evaluated as the possible working fluids for cooling the microprocessors.
HFC134a and HFC245fa were found to be the best choices for
the desired application. ª 2010 Elsevier Ltd and IIR. All rights reserved.
|
Refroidissement des
microprocesseurs a` l’aide de la microe´vaporation : un cycle de
refroidissement diphasique et innovant
Mots cle´s : Refroidissement
; Composant ; E´lectronique ; Microprocesseur-conception ; Comparaison ;
Circuit frigorifique ; COP ; Re´cupe´ration de chaleur
* Corresponding author.
Tel.: þ41 21 693
5894; fax: þ41 21 693
5960. E-mail address: jackson.marcinichen@epfl.ch (J.B.
Marcinichen).
0140-7007/$ e see front matter ª 2010 Elsevier Ltd and IIR. All
rights reserved. doi:10.1016/j.ijrefrig.2010.06.008
1. Introduction
Cooling of data
centers causes estimated annual electricity bills of 1.4 billion dollars in the
United States and of 3.6 billion dollars world wide (Koomey,
2007). Currently, the most widely used cooling technology is
refrigerated air cooling of the data centers’ numerous servers. According to
recent articles published at ASHRAE Winter Annual Meeting at Dallas (January,
2007) typically 40% or more of the refrigerated air flow bypasses the server
racks in data centers. Furthermore, servers that are turned off or on standby
are cooled as if they were operating, wasting a significant amount of the
energy for the unnecessary flow. This poor energetic performance in one of
industries leading technological sectors is quite startling and motivates the
search for a green thermal solution
for future generations of higher performance servers that consume much less
energy to operate and cool while they also provide the possibility to recover a
large quantity of waste heat. This is the topic of research addressed here.
Current chip cooling technology
consists of conducting the
microprocessor’sJouleheatingawaythroughthesiliconchipdie itself,thenacross a
thermal interface material (TIM) toa copper or aluminum heat spreader/finned
cooling element and finally byconvectiontorefrigeratedairenteringat10e15C.Lookingat
thisonamaterialbasis,themicroprocessorcircuitryhasamass of about 5 mg, the
silicon die about 5 g and the metallic cooling element about 0.5 kg,
representing about five orders of
magnitudeintheratioofthematerialsinvolvedandthuspointsoutthe huge opportunity
to improve this whole process.
Nomenclature
Roman
CHF COP GWP
mr
mw ODP
Psuc
Pdisc
Q
Sub
Tdisc
Tevap_inlet
Tevap_outlet
Tw_inlet
Tw_outlet
Wcompressor
WCond_pump
Wpump
|
critical heat flux [W cm2]
coefficient of performance [-] global warming potential [-] refrigerant mass
flow rate [kgh1] water mass flow rate [kg h1] ozone
depleting potential [-] suction pressure [bar] discharge pressure [bar]
cooling capacity or power generated by electronic components [W] subcooling
[K] discharge temperature [C] inlet evaporating temperature [C]
outlet evaporating
temperature [C]
inlet
water temperature [C] outlet water temperature [C]
compressor
power [W] pumping power of water in the condenser [W] liquid pump power [W]
|
WSubcoole
wv
xoutlet Greek r
Dhcomp DP
DPME DhME hcycle hcycle_LP hcycle_VC
Subscripts
comp
Cond
disc
evap ME
suc
w
|
r_pump pumping power
of water in the
subcondenser [W] volumic
refrigerating effect [kJ m3]
outlet vapor quality [%]
specific mass [kg m3]
compressor enthalpy difference [kJ kg1] pressureincreaseprovided
by the liquid pump[Pa] micro-evaporator pressure drop [bar] specific cooling
capacity [kJ kg1] cycle overall efficiency [-]
liquid pump cycle overall
efficiency [-]
vapor compression cycle
overall efficiency [-]
compressor
condenser discharge evaporating micro-evaporator suction water
|
Thermal designers of data centers
and server manufacturers now agree about the long term need to improve the
cooling process by implementing liquid or two-phase cooling directly in the
server itself, eliminating the poor thermal performing air as a coolant all
together (Greenberg et al., 2006; Hannemann and
Chu, 2007; Samadiani et al., 2008). That said, there is a clear need for
a detailed design and evaluation of these new cooling strategies in order to
arrive at an improved solution. They should provide more efficient heat
transfer from the chips, memories, etc. using water-cooled or boilingcooled
elements, eliminating air as a means of heat transfer, while also reducing
energy consumption for driving the cooling system by a significant amount. Some
examples of design and evaluation of these new cooling strategies can be found
in Scott (1974), Bash (2001), Peeples (2001),
Heydari (2002), Schmidt and Notohardjono (2002), Maveety et al. (2002), Phelan
and Swanson (2004) and Suman et al. (2004).
Additionally, since data centers often dissipate on the order of
5e15 MW of heat, this makes heat
recovery an important
Data center with 64 Blades (Refrigerated air cooling vs. Twophase
on-chip cooling system)
Fig.
1 e
Comparative power supply for a data center containing 64 blades for air
cooled and two-phase on-chip cooling with and without heat recovery.
energetic and environmental issue to
consider and will greatly reduce the CO2 footprint of the data
center.
Fig. 1 shows the
comparative energy consumption required by a data center with 64 blades (325 W
per blade) when using traditional air cooling, two-phase on-chip cooling and
twophase on-chip cooling when the energy is recovered, using a vapor compression
cycle. For air cooling, it is assumed that the power required to cool the data
center is the same as that required to run the information technology equipment
(Koomey, 2007; Ishimine et al., 2009). This
is plotted as a function of the compressor overall efficiency. It is seen that,
if no heatwasrecovered,thecostofcoolingthedatacenterwouldbe approximately 59%
that of traditional air cooling when
operatingatacompressorwithanoverallefficiencyof60%,whichis typical of light
commercial systems. However, if the heat was
toberecoveredandconsidering60%ofrecoveryefficiency,this value drops down to
about 24% that of traditional air cooling. These results show that the cost of
cooling could be drastically decreased when using on-chip cooling, representing
a huge potential for the next generation of data centers cooling systems.
Recent publications show the development of primarily four
competing technologies for cooling chips (all with their own pros and cons):
microchannel single-phase flow, porous media flow, jet impingement cooling and
microchannel twophase flow (Agostini et al., 2007).
Single-phase liquid cooling is now fairly well known and can be used to remove
high heat fluxes. Leonard and Phillips (2005) showed
that the use of such new technology for cooling of chips could produce savings
in energy consumption of over 60%. Despite the potential of this
technology,itsapplicationseemslimitedsofarduetotheneed of a high pumping power
to keep the temperature gradient in the fluid from inlet to outlet within acceptable
limits. Moreover,theworkingfluidmodeledinmoststudiesisusuallypure water, which
presents a problem with its high freezing point, and hence the even higher
pressure drop/pumping power of watereglycol mixtures, the real liquid
working fluid, has to be dealt with for realistic evaluations. Furthermore,
manufacturers are reluctant to use water-based fluids directly in their servers
and mainframes due to reliability questions.
The use of a porous media with single-phase and twophase
flow has as the main advantage of the large surface area for heat transfer.
Nevertheless, a high pumping power remains as a limitation. Jet impingement is
another promising cooling solution that can reach low thermal resistances
without any thermal interface and yield nearly uniform surface temperatures
with multiple jets requiring potentially high pumping power. However, possible
problems related to surface erosion as a consequence of the continuous
impingement of the high velocity jets needs to be further investigated.
Finally, two-phase flow in microchannels, i.e. evaporation
of dielectric refrigerants, is a promising medium to long term solution,
despite the higher complexity involved. This solution consumes a low pumping
power (only 1/10 as much as water cooling according to Hannemann
et al., 2004), has good temperature uniformity (Agostini
et al., 2008), very high heat transfer coefficients (as high as 270 000
W m[1]
K1 according to Madhour et al., in
press), and provides high heat flux dissipation. Studies demonstrate
that the thermal resistance decreases with increasing heat flux and with
decreasing hydraulic diameter. Possible problems with flow instabilities have
been resolved using micro-orifices at the channel inlets (Agostini et al., 2007) while the prediction
methods of local heat transfer coefficients (Consolini
and Thome, 2010), the critical heat flux (Mauro
et al., 2010), and pressure loss (Cioncolini
et al., 2009) in the two-phase region are still improving. On the other
hand, published tests using water evaporating in microchannels to cool computer
chips are not a viable solution (too low absolute pressure and vapor density at
60 C relative to the ensuing pressure drop and speed of sound) and hence this
fluid is not considered here.
Marcinichen and Thome
(2010) showed results of a
simulationcodeforsingle-phaseliquidwaterandtwo-phaseHFC134a cooling cycle, both
with a liquid pump as the driver. The liquid water cooling cycle presented a
pumping power consumption 16.5 times that obtained for the two-phase HFC134a
cooling cycle, considering a design of components and piping so that
thetotalpressuredropinthecyclewasabout1bar.Theresults permitted them to
conclude that the two-phase HFC134a
coolingcyclecanoperateatamuchlowerenergyconsumption compared with a
single-phase liquid water cooling cycle. This result can be considered a
differential when compared with demonstration projects, such as that for the
new supercomputer called AQUASAR (Ganapati, 2009),
which considers the implementation of a liquid water cooling cycle on a rack
cabinet with power consumption of around 10 kW.
In this context, the objective of the present study is
to proposeandanalyzepotentialtwo-phasecoolingcyclesableto maintain the
temperature of the chip below its upper operating limit and to recover energy
from the cycle’s condenser
forexternalapplications,suchasheatingabuilding,residence,
hospital,preheatingofboilerfeedwater,etc.Themainfocusis to work with two-phase
flow of dielectric refrigerants, using a liquid pump or a vapor compressor to
drive the fluid, which can reduce the demand for cooling energy by an
impressive amount compared to the large refrigeration chillers currently used
to cool air in data centers. A specific analysis of the potential working
fluids for this application and the results of critical heat flux obtained with
mathematical models developed for micro-evaporators are presented. Also,
qualitative and quantitative comparisons of the cooling cycles proposed are
made here, using the cycle overall efficiency and the potential for heat
recovery as the factors of merit.
had a mass flow
rate, a pumping power and a condenser size that were 4.6, 10 and 2 times
smaller than the water-cooled system. The coolant temperature rise was 10 C for
the water but negligible for HFC134a. In their study, a demonstration radar
cooling unit was also designed and built for a 6.4 kW heat load (sixteen 400 W
cold plates with convoluted fins). For 25 C ambient air temperature, the
working fluid saturation temperature was maintained at 32 C with a total
volumetric liquid flow rate of 376 L h1 and a cold plate outlet
vapor quality of 30%, providing a safety factor for dry-out. The system was
stable, easily controllable and provided essentially isothermal conditions for
all the cold plates. They emphasized the significant benefits from efficiency,
size and weight that were provided with the PLMC solution.
Mongia
et al. (2006) designed and built a small-scale refrigeration system
applicable for a notebook computer. The system basically included a
minicompressor, a microchannel condenser, a microchannel evaporator and a
capillary tube as the throttling device and is considered to be the first
refrigeration system developed that can fit within the tight confines of a
notebook and operate with high refrigeration efficiencies. HC600a (isobutane)
was the working fluid, chosen from an evaluation of 40 candidate refrigerants.
According to them, HC600a presented the best efficiency at a low pressure ratio
and was readily available, although flammable, but the system required only a
very small fluid charge (a few milliliters). Two evaporators were used, the
first one a microchannel evaporator to cool the high heat flux component (chip)
and the second one a superheater (conventional finned evaporator) to cool lower
heat flux components, such as memories, which also guaranteed that superheated
vapor was delivered to the minicompressor inlet. Two thermal test vehicles were
used to simulate the chip and the power components. For a baseline operating condition,
when the evaporator and condenser temperatures and the heat load were 50 C, 90
C and 50 W, the coefficient of performance (COP)
obtained was 2.25. The COP reached
3.70 when the evaporator and condenser temperatures increased and decreased by
10 C from the baseline conditions and the heat load was reduced to 44 W. The
smallscale refrigeration system achieved 25e30% of the Carnot efficiency (ideal COP for a Carnot cycle), values
comparable with those obtained in today’s household refrigerators.
Trutassanawinetal.(2006)designed,builtandevaluatedthe
performance of a miniature-scale refrigeration system (MSRS)
suitableforelectronicscoolingapplications.TheirMSRShadthe following components:
a commercial small-scale compressor, a microchannel condenser, a manual needle
valve as the expansion device, a cold plate microchannel evaporator, a heat
spreader and two compressor cooling fans. A suction
accumulatortoavoidliquidflowtothecompressor,anoilfiltertoreturn oil to the
compressor and guarantee good lubrication, and heat sources to simulate the
chips were also installed. HFC134a was the working fluid. System performance
measurements were conducted at evaporator temperatures from 10 C to 20 C and
condenser temperatures from 40 C to 60 C. The cooling capacityofthesystemvariedfrom121Wto268WwithaCOPof 1.9e3.2 at pressure ratios of 1.9e3.2.
Their MSRS was able to dissipate CPU heat fluxes of approximately 40e75
W cm2 and keep the junction temperature below 85 C for a chip size
of
1.9 cm2.
It was concluded that a new compressor design for electronics cooling
applications was needed to achieve better
performanceofthesystem(themostsignificantlossesoccurred in the compressor,
which was not designed for the operating conditions of electronics cooling). It
was also recommended to study the development of an automatic expansion device
and a suitable control strategy for the MSRS.
Trutassanawin et al. (2006) also
mentioned some alternative cooling approaches such as heat pipes, liquid
immersion, jet impingement and sprays, thermoelectrics and refrigeration. For
refrigeration, the following possible advantages were cited: (i) one of the
only methods which can work at a high ambient temperature, (ii) chip to fluid
thermal resistances are considerably lower, resulting in lower junction
temperatures, which could lead to higher heat fluxes being dissipated, and
(iii) lower junction temperatures can also increase the microprocessor’s
performance and increase the chip’s reliability. Possible “disadvantages” were
characterized to be: (i) an increase in the complexity and cost, (ii) possible
increase in the cooling system volume and (iii) uncertainties in the system
reliability (moving parts in the compressor).
Thome et al. (2007) surveyed
the advances in thermal modeling for flow boiling of low-pressure refrigerants
in multimicrochannel evaporators for cooling of microprocessors. According to
them, multi-microchannel evaporators hold promise to replace the actual
air-cooling systems and can compete with water cooling to remove high heat
fluxes, higher than 300 W cm2, while maintaining the chip safely
below its maximum working temperature, providing a nearly uniform chip base
temperature (Agostini et al., 2008) and
minimizing energyconsumption.Variablessuchascriticalheatfluxes,flow boilingheattransfercoefficientsandtwo-phasefrictionfactors
were evaluated and characterized as important design parameters to the
micro-evaporator for high heat flux applications.
Thome and Bruch (2008) simulated
two-phase cooling elements for microprocessors with micro-evaporation. Heat
fluxesof50Wcm2 and150Wcm2 inamicro-evaporator with
channels 75 mm wide, 680 mm high and 6 mm long with 100 mm
thick fins were simulated for flow boiling. The size of the chip was assumed to
be 12 mm by 18 mm and the micro-evaporator was considered with the fluid inlet
at the centerline of the chip and outlets at both sides, i.e. a split flow
design to reduce the pressure drop but increase the critical heat flux. Results
of pumping power, critical heat flux, and junction and fluid
temperaturesweregeneratedforHFC134aataninletsaturation temperature of 55 C
(chosen to allow for heat recovery). The
followingconclusionswerereached:i)theinfluenceofmassflux on the fluid, chip and
wall temperatures was small, ii) for the heatflux of 150 W cm2, the
chip temperature was 70C orless,
i.e.wellbelowitsoperationallimitof85C,iii)fortheheatfluxof 150 W cm2,
the junction-to-fluid temperature difference was only 15 K, which is lower than
that with liquid cooling systems, iv)thefluidtemperaturecouldstillberaisedby10Ktoajunction
temperature of 80 C while rejecting heat at 65 C for reuse, and v) the critical
heat flux increased with the mass flux and the lower limit was about 150 W cm2
for 250 kg m2 s1. The channel width had a
significant effect on the wall and junction temperatures, and there was a
turning point at about 100 mm when considering 1000 kg m2 s1
of mass flux and 150 W cm2 of base heat flux, at which these
temperatures reached a minimum. For the same mass flux and base heat flux, the
reduction of channel width also reduced the energy consumption to drive the
flow (pumping power).
From a system viewpoint, Thome
and Bruch (2008) showed an approximate comparison of performances of
liquid water cooling versus two-phase cooling. For the same pumping power
consumption to drive the fluids, two-phase cooling allowed the chip to operate
about 13 K cooler than water cooling or it could operate at the same junction
temperature but consume less pumping power using a lower refrigerant flow rate.
The two-phase cooling system appeared to be more energy-efficient than
classical air-cooling or direct liquid cooling systems while also exhausting the
heat at higher reusable temperatures. Regarding the choice between a pump and a
compressor as the driver for a micro-evaporation heat sink system, they
emphasized that the choice depends on the economic value of the re-used energy.
The system with a compressor is ideal for energy reuse because of the higher
heat rejection temperature; however the additional energy consumed by the
compressor compared to the pump has to be justified by the reuse application.
Mauro et al. (2010) evaluated
the performance of a multimicrochannel copper heat sink with respect to
critical heat flux (CHF ) and
two-phase pressure drop. A heat sink with 29 parallel channels (199 mm
wide and 756 mm deep) was tested experimentally with a split flow system
with one central inlet at the middle of the channels and two outlets at either
end. Three working fluids were tested (HFC134a, HFC236fa and HFC245fa) and also
the parametric effects of mass velocity, saturation temperature and inlet
temperature. The analysis of their results showed that a significantly higher CHF was obtainable with the split flow
system compared to the single inlet-single outlet system (Park and Thome, 2010), providing also a much lower
pressure drop. For the same mass velocity, the increase in CHF exceeded 80% for all working fluids evaluateddueto
theshorterheatedlengthof asplitsystemdesign. For the same total refrigerant
mass flow rate, an increase of 24% for HFC134a and 43% for HFC236fa were
obtained (no comparabledatawereavailableforHFC245fa).Theyconcluded that the
split flow system had the benefit of much larger CHF values with reduced pressuredrops and further developments in
the design of split flow system could yield an interesting energetic solution
for cooling of computer chips. Fig. 2 shows
the details of the two configurations of multi-microchannel copper heat sink
regarding the inlet and outlet flow system.
Fig. 2 e Schematic of micro-evaporator: a)
one inlet/one outlet and b) one inlet/two outlets.
|
Itisworthnotingthatthefocusoftheabovestudieswasthe development
of multi-microchannels evaporators able to
remove “in loco” the heat load generated by
the microprocessors and also the development of two-phase cooling systems able
to: i) control the operating conditions in the micro-evaporator, ii) maintain
the microprocessor temperature at acceptable levels, iii) recover the heat for
a secondary process and iv) operate at a much lower pump energy consumption
compared with a single-phase liquid water cooling system.
3. Present work
Three micro-evaporator cooling cycles are
proposed here:
1. one
with a liquid pump as the driver of the working fluid,
2. one
with a vapor compressor as the driver of the workingfluid, and
3. one
hybrid cycle that is a combination of the first twocycles.
The main characteristics of each cycle are presented below
with a focus on their advantages and the functions of the components.
Additionally some simulations are presented showing the following: (i)
performance of the vapor compression cooling cycle for four refrigerants as the
possible working fluids for cooling the microprocessors, (ii) operational
limits for one specific geometry of a micro-evaporator (critical heat flux,
outlet vapor quality, pressure drop, etc) to demonstrate its suitability for
this type of application, and (iii) potential for heat recovery and the cycle
overall efficiency for the first two cycles proposed.
3.1. Two-phase micro-evaporator cooling
cycle
Figs. 3e5
depict the cycles with a liquid pump, a vapor compressor and hybrid of
these two, respectively. The goal is to control the chip temperature to a
pre-established level by controlling the inlet conditions of the
micro-evaporator (pressure, subcooling and mass flow rate). It is imperative to
keep the micro-evaporator (ME) outlet vapor quality below that of the critical
vapor quality, which is associated with the critical heat flux. Due to this
limitation, additional latent heat is available, which can be used by other
heat generating components. The critical heat flux and outlet vapor quality are
Fig. 3 e Schematic of the liquid pump cooling
cycle.
Fig. 4 e Schematic of the vapor compression
cooling cycle.
predicted using methods developed by Revellin and Thome (2008), which are a function of
micro-evaporator inlet conditions and microchannel dimensions.
Another parameter that must be controlled is the condensing
pressure (condensing temperature). The aim is, during the winter, to recover
the energy dissipated by the refrigerant in the condenser to heat buildings,
residences, district heating, etc. In order to accomplish this, the idea is to
use a variable speed compressor and an electric expansion valve, as will be
discussed below.
Fig. 3 depicts the
two-phase cooling cycle where the flow rate is controlled by a liquid pump. The
P-h diagram (Fig. 6), which was drawn for
low pressure refrigerant HFC245fa, shows the thermodynamic conditions for
specific points along the cooling cycle, considering 9.9 K and 60 C for the
subcooling and evaporating temperature at the ME inlet, respectively. The
pressure drops in the micro-evaporator and microchannel cooling plate for the
memory chips (MPM) were simulated to be on the order of 0.5 bar and
0.0 bar (it is negligible), respectively, based on preliminary calculations.
These values are representative and were defined only for cycle interpretation.
The components considered and their main functions are presented below:
a) Variable
speed liquid pump: controls the mass flow ratecirculating in the system.
b) Stepper
motor valve: controls the liquid flow rate tocontrol the outlet vapor quality
in each micro-evaporator (0%e100%).
c) Micro-evaporator
(ME): transfers the heat generated by themicroprocessor to the refrigerant.
d) Microchannel
cold plate for memories (MPM): additional component used to cool the
memories using the remaining latent heat, which is available due to the
limitations enforced on the micro-evaporator.
e) Pressure
control valve (PCV): controls the condensingpressure.
Fig. 5 e Schematic of the hybrid cooling
cycle highlighting the possibility of interchangeability between liquid pump
and vapor compression cooling cycle.
|
f) Condenser:
counter-flow tube-in-tube exchanger or a micro-condenser.
g) Liquid
accumulator: guarantees that there is only satu-rated liquid at the subcooler
inlet, independent of changes in thermal load.
h) Temperature
control valve (TCV): controls the subcoolingat the inlet of liquid pump.
This cycle is characterized in having low initial costs, a
low vapor quality at the ME outlet, a high overall efficiency, low maintenance
costs and a low condensing temperature. This is a good operating option when
the energy dissipated in the condenser is not recovered, typically during the
summer season. However, the heat can still be recovered if there is an
appropriate demand for low quality heat (low exergy).
Fig. 6 e HFC245fa P-h diagram showing the
thermodynamic conditions for specific points of the liquid pump cooling cycle.
Fig. 4 shows a
two-phase cooling cycle where a vapor compressor is the driver of the working
fluid. The P-h diagram (Fig. 7), which was
also drawn for low pressure refrigerant HFC245fa, shows the thermodynamic
conditions for specific points along the cooling cycle, considering 0.69 K and
60 C for the subcooling and evaporating temperature at the ME inlet,
respectively. The pressure drops in the ME and MPM were considered
to be the same as for the liquid pump cycle above. The components considered
and their main functions are:
a) Variable
speed compressor: controls the ME inlet pressureand consequently the level of
inlet subcooling.
b) Pressure
control valve (PCV): controls the condensingpressure.
c) Condenser: counter-flow tube-in-tube exchanger or
a micro-condenser.
Fig. 7 e HFC245fa P-h diagram showing the
thermodynamic conditions for specific points of the vapor compression cooling
cycle.
Fig. 8 e Effect of superheating at the inlet
of the VSC on the isentropic COP.
d) Liquid
accumulator: guarantees that there is only satu-rated liquid at the internal
heat exchanger (iHEx1) inlet.
e) Internal
heat exchanger liquid line/suction line (iHEx1):increases the performance of
the cooling system. Fig. 8 shows the ratio
of the isentropic COP with
superheating at the inlet of the VSC relative to the saturation COPsat (as defined by Gosney, 1982). Condensing and evaporating
temperatures of 60 C and 90 C were considered, respectively. It is worth noting
that for the four potential working fluids analyzed, the ratio increases with
superheating, although some fluids, such as ammonia, shows decreasing
performance (Gosney, 1982).
f) Electric
expansion valve (EEV): controls the low-pressurereceiver level.
g) Lowpressurereceiver
(LPR):this componentcan be seen asa second internal heat exchanger liquid
line/suction line, which increases the EEV inlet subcooling and allows an
overfeed to the ME since the ME outlet returns to this receiver. The same
analysis considered for the iHEx1 can be considered here, i.e. the LPR
increases the performance of the cooling system as it, together with the iHEx1,
generates the superheating and the subcooling at the inlet of the VSC and EEV,
respectively.
h) Stepper
motor valve: controls the liquid flow rate tocontrol the outlet vapor quality
in each micro-evaporator (0%e100%).
i) Micro-evaporator
(ME): transfers the heat away from the microprocessor.
j) Microchannel
cold plate for memories (MPM): cools thememories.
This cycle is characterized by a high condensing temperature
(high heat recovery potential), a high range of controllabilityof theME
inletsubcooling (characteristic ofsystemswith VSC and EEV), a medium overall
efficiency when compared with the liquid pumping cooling cycle (uncertain,
evaluate potential for heat recovery in the condenser). This is a good
operating option when the energy dissipated in the condenser is recovered for
other use, typically during the winter season when considering a district heating
application (high exergy).
Fig. 5 considers a hybrid
two-phase cooling cycle, i.e. this multi-purpose cooling cycle makes it
possible to interchange the cycles driven by the liquid pump and the vapor
compressor. The change of cycle would be accomplished through the shut off
valves 1e7 (SOV). The decision on the cooling cycle to operate would
depend on demand for the heat recovered, or allow for cycle maintenance (repair
of the compressor or pump). The microprocessors cannot operate without cooling
and thus the interchangeability of the cycles represents a safety mechanism in
case of failure of the pump or compressor. The “cons” of the hybrid cycle would
be mainly the higher initial cost but certainly the advantages (system online
reliability, controllability, cycle interchangeability and flexibility in heat
recovery) may prove to justify the higher initial cost. Furthermore, this
hybrid cycle represents a plugand-play option
where any one of the three cycles can be installed based on the particular
application, minimizing engineering costs.
Fig. 9 e Typical blade with two
microprocessors and a heat generation capacity higher than 300 W.
|
It is worth mentioning that the applicability of these
cooling cycles is not restricted to only one microprocessor but can be applied
to blade servers and clusters, which may have up to 64 blades per rack cabinet.
Each blade, such as that shown in Fig. 9,
can have two (or more) microprocessors with a heat generation capacity higher
than 150 W. If the auxiliary electronics (memories, etc.) on the blade are
included, the total heat generation per blade can be higher than 300 W. Thus,
the microchannel cold plate (MPM) described in the cooling cycles
has the function to cool the auxiliary electronics that can represent about 60%
of the total heat load on the blade, but have a larger surface area compared to
the CPU and thus a lower heat flux.
Finally, when considering an entire rack, a very sizable
heat loadis generated,which representsa good opportunity to recover the heat
rejected. In this case, reuse of the heat removed from the blades for a
secondary application will greatly reduce the CO2 “footprint” of the
system. For example, if we consider a data center with 50 vertical racks, where
each rack has 64 blades and each blade dissipates 300 W, the total potential
amount of heat to be recovered will be 0.96 MW. Such a heat recovery system requires
a secondary heat transfer fluid to pass through all the condensers (either
water or a refrigerant) and then transport the heat to its destination. 3.2. Working fluids
Thepresenceofoil inthe
coolingcycleswouldadverselyaffect the performance of the heat exchangers and
also possibly lead toproblemsofcloggingofsmallcomponentsandgenerationof
contaminants (Marcinichen, 2006). So, for
this reason, these cyclesshoulduse drivercomponents that do not requireoil for
lubrication purposes (that is, an oil free liquid pump and/or an oil free vapor
compressor should be used).
Table 1 shows a
comparison of four refrigerants in relation to their environmental parameters (BNCR35, 2008), where GWP is the global warming potential (ratio of the warming caused by
the substance to the warming caused by a similar mass of carbon dioxide, GWP ¼ 1 for CO2) and ODP is the ozone depleting potential
(ratio of the impact on ozone of a chemical compared to the impactof a
similarmassof CFC11, ODP¼ 1
for CFC11). It is worth noting that the refrigerants considered have an ODP of zero, but still have rather high
values of GWP.
The four working fluids (HFC236fa, HFC245fa, HFC134a and
HC600a-isobutane) were evaluated with regard to COP and the volumic refrigerating effect for the vapor compression
cooling cycle proposed (Fig. 4). The cycle
considers two microchannel cooling components, ME and MPM, the first
to cool the microprocessor (outlet vapor quality set to 30%) and the second to
cool the auxiliary electronics (memories, DC/DC, etc) on the blade
microprocessor (outlet vapor quality set to 90%, which is the estimated value
that considers the blade manufacturer’s information that the auxiliary
components
Table1 eEnvironmental parameters GWPandODP for the four potential
working fluids.
|
Refrigerant GWP (100 year) ODP
|
HFC236fa 6300 0 HFC245fa
950 0
HFC134a 1300 0
HC600a 3 0
|
Table
2 e Boundary conditions
for the working fluids analysis on the vapor compression cooling cycle.
|
1) Condenser
> condensing temperature ¼ 90 C, outlet vapor quality ¼ 0%
2) Micro-evaporator
on chip (ME)
> inlet saturation temperature ¼ 60 C,
>outlet vapor quality ¼ 30%
3) Microchannel
cold plate on memories (MPM)
> outlet vapor quality ¼ 90%
4) Effectiveness
of iHEx1 ¼ 90%
5) Input data
> fluids: HFC245fa, HFC236fa, HFC134a and HC600a
> total pressure drop in the two evaporators
(ME and MPM) ¼ 0.5 bar
6) Outlet
data
> discharge temperature (isentropic compression)
> enthalpy difference in the two evaporators and in the
compressor
> volumic refrigerating effect (qualitative idea of
compressor size)
>COP
|
can represent up to 65% of the total
heat load). It was also considered that iHEx1 has an effectiveness of 90% and
the two microchannel cooling components have a total pressure drop of 0.5 bar.
The volumic refrigerating effect (wv) is determined by calculating the ratio between the
sum of the ME and MPM enthalpy differences and the specific volume
in the compressor suction (Gosney, 1982).
This parameter indicates comparatively the size of compressor for the different
working fluids, i.e. a higher volumetric refrigerating effect means that a
smaller swept volume rate is required for a particular cooling capacity.
Table 3 shows the
results considering the conditions in Table 2.
For this cycle, the COP was
determined by dividing the sum of the ME and MPM enthalpy
differences (DhME) by
the compressor enthalpy difference (Dhcomp).
It can be observed that HFC245fa has the lowest suction and discharge pressures
(Psuc
and Pdisc), which is
advantageous for the compressor and cooling system (allows a less robust construction
that enables material cost savings). However, it also has a lower volumic
refrigerating effect, meaning that a larger compressor will be necessary. The
best working fluid, when looking at the volumic refrigerating effect, is
HFC134a since its value is more than 2 times higher than that of HFC245fa, but
requires operation at a higher Psuc
and Pdisc. It is
worth noting that HC600a (isobutane) has the highest specific cooling capacity
(DhME), as shown in Fig. 10, implying lower mass flow rates for
the same cooling capacity.
Relatively small differences in COP are observed in Table 3 for
the four fluids, showing no significant effect on the choice of the working
fluid. The same can be said about the compressor discharge temperature (Tdisc). The high values of COP observed are justified by the fact
that the thermodynamic analysis does not consider the irreversibilities
inherent in the cycle. However, due to the high evaporating temperatures
considered here (for attaining a high
performance green
HC600a
h,kJ/kg
Fig. 10 e HC600a P-h diagram highlighting the
large specific cooling capacity.
computing solution), the COP values are higher than those found
in household refrigerators and light commercial systems (actual COP about 2 or 3). Finally, it can be
observed that HC600a and HFC134a present the lowest pressure ratios, which is
an advantage because they represent compressors with high volumetric
efficiencies.
Fig. 11
shows the effects of iHEx1 effectiveness and condensing temperature on
the cycle COP. The same conditions
described in Table 2 were considered and
HFC134a was used as working fluid. It can be observed that the COP increases when the iHEX1
effectiveness increases. However, the condensing temperature has a greater
effect on the COP, decreasing with an
increase of condensing temperature. It is worth mentioning that there might be
an optimal condensing temperature to obtain the maximum economical value of
recovered heat for the penalty paid in compressor power consumption.
ME must be able to maintain the
microprocessor’s operating temperature from 70 C to 75 C (83 C is the nominal
maximum operating temperature).
Basedontheaforementionedinformation,Table4showsthe
results obtained by the methods developed to evaluate the performance of the
ME’s. The three-zone model (Thome et al., 2004)
was used for two-phase heat transfer since it was shown to predict many fluids
and geometries with good accuracy (Dupont et al.,
2004), the numerically based model of Revellin
and Thome (2008) was used for critical heat flux calculations and the
homogeneous model was used for two-phase pressure
dropssinceitwasfoundtopredictmicrochannelpressuredrops
withrelativelygoodaccuracy(Ribatskietal.,2006).Themethods
werealsousedtoestimatethemassflowrateintheME.Theheat load was considered to
vary between 90% and 100%, i.e. from 146.25W to162.50 W. The ME inlet
subcooling, Sub, wasfixed at
5 K and two inlet evaporating temperatures, Tevap_inlet, were considered,
50 C and 60 C. The dimensions of the ME were 170mmoffinwidthandchannelwidthand1700mmoffinheight,
with a heated “footprint” of 18.5 mm by 13.5 mm. The working fluid selected for
the present analysis was HFC134a.
The results show that the mass flow rate, mr, to guarantee the cooling
capacity must be from 10.82 kg h1 to 11.90 kg h1 when the
outlet vapor quality, xoutlet,
is 30% and the inlet evaporating temperature is 60 C. For this case the lowest
critical heat flux, CHF, was 141.2 W
cm2, a value well above the actual value of 65 W cm2 (safety
factor of 2.2). However, when the outlet vapor quality was set to 50%, the
smallest CHF was then only 83.1 W cm2,
a value judgedto be too nearto the actual value for the standard blade (65 W cm2)
since the accuracy in predicting CHF is
about 20%. Thus, it is best to consider an outlet vapor quality of 30%. While
not done here, it is also possible to use the one-dimensional numerical method
of Revellin and Thome (2008) to analyze the
CPU die’s power dissipation map to verify the local safety factors in CHF with respect to the local hot spots.
3.4. Analysis of the cycle
overall efficiency and potential for energy recovery
Table 3 e Results of simulations on the vapor compression cooling
cycle/potential working fluids.
|
|
|||||||
|
Dhcomp (kJ kg1)
|
|||||||
HFC236fa
|
8.0
|
110.9
|
15.65
|
7.14
|
2.19
|
104.0
|
4333
|
13.0
|
HFC245fa
|
8.3
|
110.9
|
10.04
|
4.14
|
2.43
|
150.0
|
3010
|
18.1
|
HFC134a
|
7.0
|
119.2
|
32.47
|
16.33
|
1.99
|
112.7
|
7736
|
16.1
|
HC600a
|
8.4
|
111.1
|
16.14
|
8.10
|
1.99
|
250.5
|
4566
|
30.0
|
The overall efficiencies (hcycle) of the proposed cycles were evaluated considering the potential for energy recovery. This is determined by the ratio of the recovered energy in the condenser and subcooler to the energy consumed to drive the working fluid. Some additional terms were also considered to take into account the pumping power of the secondary fluid in the condenser and subcooler. Thus, considering the possible heat recovery in the heat exchangers, hcycle will be influenced by the type of heat recovery application, since different types
Effects of iHEx1 and condenser on the cycle COP
Fig. 11 e Effects of iHEx1 effectiveness and
condensing temperature on the cycle COP.
of condensers, subcoolers and condensing
temperatures could be chosen to maximize hcycle for the particular
situation.
For an ideal case, the power dissipated by the microprocessor
and memories, QMEþMPM,
and the power consumed by the compressor, Wcompressor,
or the liquid pump, Wpump,
are fully recovered in the condenser and subcooler. This also holds for the
power consumed by the pumps associated with the secondary fluid in the
condenser, WCond_pump, and
subcooler, WSubcooler_pump.
The cycle overall efficiency for the liquid pump and vapor compression cycle
can, therefore, be written as:
a) Liquid
pump cyclehcycle LP ¼ QMEþMPM þ Wþpump þ WCond pump þ WSubcooler pump
Wpump WCond pump þ WSubcooler pump
¼ þ þ QMEþMPM (1)
1
Wpump WCond pump þ WSubcooler pump
b)
Vapor compression cycle
QMEþMPM þ WCompressor þ WCond pump
Presently, we are not concerned with
the performance of the secondary system heat exchanger, which will be a
function of its unknown (for now) mass flow rate and fluid properties. As noted
in Eqs. (1) and (2), the hcycle
will depend mainly on the pumping power of the secondary fluid, which in
itself is a function of the type of application of the secondary system (heat
exchanger size, type and properties of the secondary fluid). It is worth noting
that the difference in cycle overall efficiency for the two cycles is in the
denominator. In general, the compressor power is higher than the liquid pump
power, due to the work needed to obtain a differential pressure associated with
the compressor. This could lead to the conclusion that the hcycle
for the liquid pump cycle is always higher than for the vapor compression
cycle. However, the pumping power of the secondary fluid through the condenser
is higher for the liquid pump cycle than for
the other cycle because of the lower condensing temperature, with the
possibility of the opposite to be true. Furthermore, the hcycle
will depend on the efficiency of each component and on the end use of the
energy recovered in the condenser and subcooler.
The results of a simplified analysis evaluating the
potential of heat recovery for the cycles with the liquid pump and the vapor
compressor are depicted in Table 5. To
develop this analysis, the results in the second line of Table 4 were taken into consideration as well as
the following assumptions:
a) water
was considered as the secondary fluid,
b) the
condenser and subcooler water pumping powers werenot considered,
c) the
HFC134a liquid pumping power was determinedthrough Eq. (3)
for 100% liquid pump overall efficiency. The liquid pump inlet
subcooling was considered 10 K and the inlet pressure was considered that at
the ME outlet,
d) the
compressor suction pressure was considered to be thesame pressure as at the ME
outlet and with 10 K of
superheating,
e) the
vapor compression was considered isentropic and100% compressor overall
efficiency, vapor compression cycle,
Table
4 e Operational limits
for one micro-evaporator. HFC134a as working fluid.
|
Boundary conditions in the
micro-evaporator (working fluid: HFC134a)
Tevap_inlet (C) Sub (K) xoutlet (%) Qw mr (Kg h1) DPME (bar) Tevap_outlet (C) CHF (W cm2)
|
50 5 30 162.50 10.82 0.0092 50.0 145.7
60 5 30 162.50 11.90 0.0096 59.9 148.9
50 5 30 146.25 10.28 0.0082 50.0 141.2
60 5 30 146.25 10.82 0.0082 59.9 141.2
50 5 50 162.50 7.03 0.005 50.0 91.9
60 5 50 162.50 7.57 0.005 59.9 91.2
50 5 50 146.25 6.28 0.0045 50.0 83.3
60 5 50 146.25 6.76 0.0043 59.9 83.1
|
Table 5 e Comparative analysis for the liquid pump and vapor compression cooling
cycle regarding heat recovery.
|
Cycle Energy
recovery (W) Tw_inlet (C) Condenser Subcooler
Tw_outlet (C) mw (Kg h1) Tw_outlet (C) mw (Kg h1)
|
Liquid pump 162.5 30 49.9 4.85 49.9 2.18
Vapor compressor 206.7 30 80.0 3.56 e e
|
h) the condenser and subcooler outlet
water temperature was assumed to be 10 K less than the condensing
temperature,
The refrigerant pumping power is thus
calculated as:
m
Wpump ¼DP (3)
r
where m is the mass flow rate, r is
the specific mass and DP is the pressure
increase provided by the pump.
In Table 5, it can be
observed that there is an increase of 27.2% of heat recovery for the vapor
compression cycle (this additional heat is associated with that imparted by the
compressor) while there is an increase of 98% of total water mass flow rate, mw, for the liquid pump cycle
that is associated with a lower water temperature difference in the condenser
and subcooler. The final result shows that the liquid pump cycle will require a
larger pump to circulate water in the condenser and subcooler, i.e. a higher pumping
power and possibly a larger heat exchanger (condenser þ subcooler).
Finally, it is important to remember that the results presented above are only
for a simple example case and that a more detailed analysis considering all
components and their thermal efficiencies needs to be done to better understand
the behaviorand performance of eachcycle and its particular heat recovery
application.
4. Conclusion
1. Three
two-phase cooling cycles for cooling of data centerservers have been proposed
for more energy-efficient cooling of blade server microprocessors and their
memories. The cycles use two-phase boiling in microchannels for removing the
heat from the microprocessors and memories and the heat can be dissipated
either to the ambient or, better, it will be recovered for heating of
buildings, preheating of boiler feed water, etc. This second solution has the
potential to be a key step in the realization of a new generation of green, high performance data centers.
2. To
integrate operating flexibility and higher system operating reliability into
one cooling cycle, include the possibility to recover heat or not, and to
facilitate maintenance while still operating the server’s cooling system, a
hybrid cooling cycle was proposed with interchangeability between the liquid
pump and vapor compression driven cooling cycles. As the cooling of the servers
should have a very high online availability, the interchangeability will
also guarantee uninterrupted operation in
case of forced maintenance of the compressor or the pump.
3. The
vapor compression cooling cycle proposed was considered to determine the best
working fluid for cooling applications of microprocessors and memories. The
analysis took into consideration the following variables: suction and discharge
pressures, volumic refrigerating effect, pressure ratio and COP. Of the four refrigerants
considered, HFC134a and HFC245fa appear to be the best choices.
4. Methods
taken from the literature to evaluate the thermalperformance of the ME’s were
used here to estimate the CHF of the
ME and compare to the total heat flux of a specific blade. For an evaporating
temperature, subcooling and outlet vapor quality of 60 C, 5 K and 30%,
respectively, the predicted CHF was
about 2.2 times the actual maximum heat flux of the blade server using fins
that were 1700 mm high, 170 mm thick and channels 170 mm
wide. This safety factor was considered sufficient since the accuracy in
predicting CHF is about 20%. For an
outlet vapor quality of 50% the factor decrease to only 1.3 times, a value
judged to be too low to guarantee problem free operation.
5. The
micro-evaporator cooling cycles proposed were
analyzedinrelationtothecycleoverallefficiency(hcycle)and the potential for
energy recovery, after the aforementioned constraint of critical heat flux was taken
into account. The qualitative comparison showed that the best cycle, i.e. that
with the highest hcycle, will depend mainly on the end application of
the energy recovered in the condenser and subcooler, which will influence the
design of the cooling cycle and the thermodynamic conditions. A quantitative
comparison showed that the vapor compression cycle is capable of recovering
more energy for a lower water mass flow rate. Also, it was shown that a higher
water temperatureisachievedwiththevaporcompressioncycleduetothe higher
condensing temperature.
Acknowledgements
The Commission for Technology and Innovation
(CTI) contract number 6862.2 DCS-NM entitled “Micro-Evaporation Cooling System
for High Performance Micro-Processors: Development of Prototype Units and
Performance Testing” directed by the LTCM laboratory sponsored this work along
with the project’s industrial partners: IBM Zu¨rich Research Laboratory
(Switzerland) and Embraco (Brazil). J.B. Marcinichen wishes to thank CAPES
(“Coordenac¸a˜o de Aperfeic¸oamento de Pessoal de N´ıvel Superior”) for a one
year fellowship to work at the LTCM laboratory.
r e f e r e n c e s
Agostini, B., Fabbri, M., Park, J.E., Wojtan, L., Thome,
J.R., Michel, B., 2007. State of the art of high heat flux cooling
technologies. Heat Transfer Engineering 28, 258e281.
Agostini, B., Fabbri, M., Thome, J.R., Michel, B., 2008. High
heat flux two-phase cooling in silicon multimicrochannels. IEEE Transactions on
Components and Packaging Technologies 31 (No 3), 691e701.
Bash, C.E., 2001. Analysis of refrigerated loops for electronics
cooling. In: Proceedings Pacific Rim/ASME Int. Electron.
Packag. Tech. Conf. Exhibition (IPACK’01), Kauai, HI, pp.
811e819.
BNCR35, 2008. Overview of New and Alternative Refrigerants.
Market Transformation Programme/Supporting UK Government Policy on Sustainable
Products. http://efficientproducts.defra.gov.uk/product-strategies/subsector/
commercial-refrigeration.
Cioncolini, A., Thome, J.R., Lombardi, C., 2009. Unified
macro-tomicroscale method to predict two-phase frictional pressure drops of
annular flows. International Journal of Multiphase Flow 35, 1138e1148.
Consolini, L., Thome, J.R., 2010. A heat transfer model for
evaporation of coalescing bubbles in micro-channel flow. International Journal
of Heat and Fluid Flow 31, 115e125.
Dupont, V.,
Thome, J.R., Jacobi, A.M., 2004. Heat transfer model for evaporation in
microchannels. Part II: comparison with the database. International Journal of
Heat and Mass Transfer 47, 3387e3401.
Ganapati,
P., 2009. Water-cooled supercomputer doubles as dorm space heater. http://www.wired.com/gadgetlab/2009/06/ibmsupercomputer/
Viewed
June 23.
Greenberg, S., Mills, E., Tschudi, B., 2006. Best Practices
for Data
Centers: Lessons Learned from Benchmarking 22 Data
Centers. ACEEE Summer Study on Energy Efficiency in
Buildings.
Gosney, W.B., 1982. Principles of Refrigeration, first ed.
CambridgeUniversity Press.
Hannemann, R., Chu, H., 2007. Analysis of Alternative Data
Center Cooling Approaches. InterPACK, Vancouver, BC, CA.
Hannemann, R., Marsala, J., Pitasi, M., 2004. Pumped liquid
multiphase cooling. In: Proceedings IMECE e International Mechanical
Engineering Congress and Exposition, Anaheim, CA, USA, paper 60669.
Heydari, A., 2002. Miniature vapor compression refrigeration
systems for active cooling of high performance computers. In:
Proceedings 8th Intersoc. Conf. Thermal Thermomech.
Phenom. Electron. Syst. (I-THERM), pp. 371e378.
Ishimine, J., Ohba, Y., Ikeda, S., Suzuki, M., 2009.
Improving IDC cooling and air conditioning efficiency. Fujitsu Scientific and
Technical Journal 45, 123e133.
Koomey, J.G., 2007. Estimating Total Power Consumption by
Servers in the U.S. and the World. Analytics Press,
Oakland, CA. http://enterprise.amd.com/us-en/AMD-Business/
Technology-Home/Power-Management.aspx
February
15.
Leonard, P.L., Phillips, A.L., 2005. The thermal bus
opportunity e
a
quantum leap in data center cooling potential. Presented at the ASHRAE Annual
Meeting, Denver, CO.
Madhour, Y., Olivier, J., Costa-Patry, E., Paredes, S.,
Michel, B., Thome, J.R. Flow boiling of R134a in a multi-microchannel heat sink
hotspot heaters for energy-efficient microelectronic CPU cooling applications.
IEEE Transactions on Components and Packaging Technologies, in press.
Marcinichen, J.B., 2006. Theoretical and Experimental Study
of the
Physical/Chemical Aspects of Capillary Tubes Clogging by
Adsorption of Polyolesther.
Doctorate Thesis, Thermal Sciences, Mechanical Engineering, Federal University
of Santa Catarina, Floriano´polis, SC, Brazil (in Portuguese).
Marcinichen, J.B., Thome, J.R., 2010. New novel green
computer two-phase cooling cycle: a model for its steady-state simulation. In:
Proceedings of the 23rd International Conference on Efficiency, Cost,
Optimization, Simulation and Environmental Impact of Energy Systems e ECOS2010,
Lausanne, Switzerland.
Mauro, A.W., Thome, J.R., Toto, D., Vanoli, G.P., 2010.
Saturated critical heat flux in a multi-microchannel heat sink fed by a split
flow system. Experimental Thermal and Fluid Science 34, 81e92.
Maveety, J.G., Brown, M.F.W., Chrysler, G.M., Sanchez, E.A.,
2002. Thermal Management for Electronics Cooling using a Miniature Compressor.
In: Proceedings Int. Microelectron.
Packag. Soc. (IMAPS), Denver, CO.
Mongia, R., Masahiro, K., DiStefano, E., Barry, J., Chen, W.,
Izenson, M., Possamai, F., Zimmermann, A., Mochizuki, M.,
2006. Small scale refrigeration system for electronics cooling within a
notebook computer. In: Proceedings ITHERM, San Diego, CA.
Park, J.E., Thome, J.R., 2010. Critical heat flux in
multimicrochannel copper elements with low pressure refrigerants.
International Journal of Heat and Mass Transfer 53, 110e122.
Peeples, J.W., 2001. Vapor compression cooling for high
performance applications. Electronics Cooling 7, 16e24.
Phelan, P.E., Swanson, J., 2004. Designing a mesoscale
vaporcompression refrigerator for cooling high-power microelectronic. In:
Proceedings Inter Soc. Conf. Thermal Thermomech. Phenom. Electron. Syst.
(I-THERM), Las Vegas, NV, pp. 218e223.
Revellin, R., Thome, J.R., 2008. A theoretical model for the
prediction of the critical heat flux in heated microchannels. International
Journal of Heat and Mass Transfer 51, 1216e1225.
Ribatski, G., Wojtan, L., Thome, J.R., 2006. An analysis of
experimental data and prediction methods for two-phase frictional pressure drop
and flow boiling heat transfer in micro-scale channels. Experimental Thermal
and Fluid Science 31, 1e19.
Samadiani, E., Joshi, Y., Mistree, F., 2008. The thermal
design of a next generation data center: a conceptual exposition.
Journal of Electronic Packaging 130.
Schmidt, R.R., Notohardjono, B.D., 2002. High-end server
lowtemperature cooling. IBM Journal of Research and Development 46, 739e751.
Scott, A.W., 1974. Cooling of Electronic Equipment. Wiley,
New York, pp. 204e227.
Suman, S., Fedorov, A., Joshi, Y., 2004.
Cryogenic/sub-ambient cooling of electronics: revisited. In: Proceedings Inter
Soc.
Conf. Thermal Thermomech. Phenom. Electron. Syst.
(I-THERM), Las Vegas, NV, pp. 224e231.
Thome, J.R., Agostini, B., Revellin, R., Park, J.E., 2007.
Recent advances in thermal modeling of micro-evaporators for cooling of
microprocessors. In: Proceedings of the ASME International Mechanical
Engineering Congress and Exposition (IMECE), Seattle, Washington.
Thome, J.R., Bruch, A., 2008. Refrigerated cooling of
microprocessors with micro-evaporation heat sinks: new development and energy
conservation prospects for green datacenters. In: Proceedings Institute of
Refrigeration (IOR).
Thome, J., Dupont, V., Jacobi, A., 2004. Heat transfer model
for evaporation in microchannels. Part I: presentation of the model.
International Journal of Heat and Mass Transfer 47, 3375e3385.
Trutassanawin,
S., Groll, E.A., Garimella, S.V., Cremaschi, L., 2006. Experimental
investigation of a miniature-scale refrigeration system for electronics
cooling. IEEE Transactions on Components and Packaging Technologies 29 (No. 3),
678e687.
Hannemann
et al. (2004) have proposed a pumped liquid multiphase cooling system
(PLMC) to cool microprocessors and microcontrollers of high-end devices such as
computers, telecommunications switches, high-energy laser arrays and high-power
radars. According to them, their system could handle applications with 100 W
heat loads (single computer chip) as well as applications with short time
periods of kW heat loads (radar). Their PLMC consisted basically of a liquid
pump, a high performance cold plate (evaporator) and a condenser with a low
acoustic noise air mover to dissipate the heat in the ambient air. A comparison
between a singlephase liquid loop (water) and the system proposed with HFC134a
wasmadefor a 200 Wheat load. The HFC134asystem
To evaluate the performance of the cooling
cycles proposed, the first step was to define a standard blade model where we
need to control the microprocessor and memory temperatures. A photograph of the
standard blade is shown in Fig. 9. According
to the manufacturer, when we consider only one microprocessor and the auxiliary
electronics associated with it, the maximum heat flux will be about 65 W cm2
and the area for heat transfer is about 2.5 cm2 (this is the
worst case, i.e. the entire heat load assumed to be concentrated on the small
area of the chip and its ME). Thus the maximum heat transfer rate will be 162.5
W per ME. The cooling capacity per
Langganan:
Postingan (Atom)