An 8-Bit, 40-Instructions-Per-Second Organic
Microprocessor on Plastic Foil
Kris Myny, Student Member, IEEE, Erik van Veenendaal, Gerwin H. Gelinck, Jan Genoe, Member, IEEE,
Wim Dehaene, Senior Member, IEEE, and Paul Heremans
Abstract—Forty years after the first silicon microprocessors, we Plastic electronics refers to the technology to make transistors demonstrate an 8-bit microprocessor made from plastic electronic and circuits with thin-film organic or plastic semiconductors technology directly ontion is as low as 100today limited to 40 instructions per second. The pW. The ALU-foil operates at a supply voltageflexible plastic foil. The operation speed isower consump- on arbitrary substrates, including not only rigas glass, but also flexible plastic foils. A variid substrates suchety of organic of 10 V and back-gate voltage of 50 V. The microprocessor can molecules and polymers have been developed as semiconducexecute user-defined programs: we demonstrate the execution of tors, and the best ones – today feature a charge carrier
the multiplication of two 4-bit numbers and the calculation of themoving average of a string of incoming 6-bit numbers. To executesuch dedicated tasks on the microprocessor, we create small plastic mobility on the order of 1–10 cmlower than that of silicon. When integrated/Vs, some 100into circuits, theto 1000 times circuits that generate the sequences of appropriate instructions. realistic mobility values are somewhat lower but nevertheless The near transparency, mechanical flexibility, and low power con- sufficient for applications such as backplanes for flexible sumption of the processor are attractive features for integration on active-matrix displays, in particular for flexible electronic everyday objects, where it could be programmed as, amongst otheritems, a calculator, timer, or game controller. papers . The first dedicated circuit applications of organic thin-film transistors have also appeared in recent years, such cessor,organic processor, organic transiIndex Terms—flexible processor, organic circuits, organic microprocessor,Dual-gate, flexible circuits,stor, plastic circuits, plasticflexible micropro- as recently demonstrated by the idriver for an organic active matrix OLED display . Such cir-ntegration of an organic line microprocessor, plastic processor. cuits can be made directly on thin and ultra-flexible plastic foils, which allows them to be very simply laminated on everyday objects, and furthermore provides appealing characteristics in
I. INTRODUCTION terms of bending radius and robustness: we no longer talk of
LECTRONICS pervades everyday life and is undeniably flexible electronics but of truly crinkable electronics .
making its way from computing to telephony and to as- Here, we investigate the possibility to use this technology to sisting us in everyday tasks through products such as electronic realize microprocessors on plastic foil. As the cost of an elecpaper to read and write, electronic noses to sense gases, smart tronic chip decreases with production volume, ultralow-cost milighting with electronics to save energy, and so on. The key en- croprocessors on easy-to-integrate flexible foils will be an enabler of these pervasive electronics applications is the fact that abler for ambient intelligence: one and the same type of chip integration of ever more transistors with ever smaller dimen- can be integrated on vastly different types of objects to perform sions has resulted in the cost of a single semiconductor tran- customized functions, such as identification, simple computing, sistor, or switch, to dwindle to the level of ten nano-dollars per and controlling.
transistor. Nevertheless, if the cost of a transistor in a chip is The organic microprocessor has been implemented as two negligible and decreasing, the cost of placing and routing elec- different foils: an arithmetic and logic unit (ALU) foil and an tronics on daily objects is not necessarily proportionally low. instruction foil. The ALU-foil is a general-purpose foil which can execute a multitude of functions. On the other hand, the in-
Manuscript received May 07, 2011; revised July 17, 2011; accepted struction foil is a dedicated chip that generates the sequence of September 05, 2011. Date of publication November 04, 2011; date of current instructions to obtain a specific function. It sends this sequence version December 23, 2011. This paper was approved by Guest Editor Satoshi of instructions to the ALU-foil such that the combination of both
Shigematsu. This work was supported in part by the EU-Projects COSMIC(ISTIP-247681) and ORICLA (FP7-ICT-2009-4 247798). foils results in the execution of a specific algorithm. The first
K. Myny is with imec, 3001 Leuven, Belgium, the Katholieke Universiteit prototype of the organic microprocessor  had only one inLeuven, 3001 Leuven, Belgium, and also with the Katholieke Hogeschool Lim- struction foil available and could operate up to six operations burg, 3590 Diepenbeek, Belgium (e-mail: email@example.com).E. van Veenendaal is with Polymer Vision, 5656 AE Eindhoven, The Nether- per second (OPS). In this paper, we report an improved organic lands. microprocessor that can run 40 OPS and can operate with two
J. Genoe is with imec, 3001 Leuven, Belgium, and also with the Katholieke different instruction foils. We first discuss the technology and
Hogeschool Limburg, 3590 Diepenbeek, Belgium.G. H. Gelinck is with the Holst Centre/TNO, 5605 KN Eindhoven, The choice of logic family used for the microprocessor foil. Sub-
Netherlands. sequently, we report on the design and measurement data of
W. Dehaene, and P. Heremans are with imec, 3001 Leuven, Belgium, and the ALU-foil. Next, a complete integrated microprocessor is also with the Katholieke Universiteit Leuven, 3001 Leuven, Belgium.Color versions of one or more of the figures in this paper are available online demonstrated by combining the ALU-foil with the instruction at http://ieeexplore.ieee.org. foil. Finally, we conclude by comparing the organic micropro-
Digital Object Identifier 10.1109/JSSC.2011.2170635 cessor to the silicon Intel 4004 early-days processor.
0018-9200/$26.00 © 2011 IEEE
back-gate as -control gate (right). (Figures from .)
II. TECHNOLOGY AND LOGIC FAMILY
In our organic thin-film transistor (OTFT) technology, all layers to make the circuits are processed directly on a 25-m-thick PEN (polyethylene naphthalate) foil and consist of polymers or organic molecules, with the exception of metals (Au) for gates, sources, drains, and interconnect lines between the transistors . The OTFT technology is a unipolar p-type, single- technology, using pentacene as semiconductor. The basic transistor has a channel length of 5 m.
The yield of larger integrated circuits in such a single-, p-type-only technology is intrinsically limited, as a result of the parameter variability . Myny et al. have demonstrated an increased circuitrobustnessby the additionofan extra gate to each OTFT, leading to the availability of multiple ’s in a unipolar p-type technology . The organic microprocessor has been designed in this technology. A cross section is shown in Fig. 1. As depicted, each TFT comprises two gates, a front gate and a back gate. The front gate controls the channel current while the back gate, which is weakly coupled to the semiconductor channel, is used to shift the transistor’s threshold voltage. This is depicted in Fig. 1. As a consequence, the of each single transistor can be independently tuned.
The key factor when determining the choice of logic family for the basic circuit gates is the circuit robustness parameterized by the noise margin. Fig. 2 shows the noise margin (at 20 V) of typical zero- inverters when no back-gate is used, compared with the noise margin achievable with an optimized dual-gate zero- topology. In this optimized topology, the back gatesoftheload transistorsareconnectedtothefrontgates, while all back gates of the drive transistors are connected to a common rail, to which a back-gate voltage is applied externally .
The typical spread on threshold voltage in organic TFT technology is 0.2 to 0.5 V, which is large compared with the noise margin achievable with single-gate technology. As a result, it is common practice in the field of organic electronics to use a transistor-level approach to design (simple) circuits. Indeed, it is usually necessary to simulate the schematic entry with an analog circuit-level simulator (such as Spectre or Spice) and use
Monte Carlo simulations to predict yield. However, such analog circuit-level simulators are not adapted to deal with the needed level of complexity to design and simulate an organic microprocessor due to the large number of (parallel) switching gates, large amount of input, control, and output signals. In contrast, in our optimized dual-gate, the much improved noise margin allows to make use of common digital design practices. Starting from the basic characteristics of inverters and other logic gates, we designed a robust library of basic digital logic gates (inverters, NANDs, buffers). This standard cell library was used to
design the organic microprocessor by means of a gate-level design approach. Therefore, after modeling, simulating, and measuring the basic building blocks, we used a gate-level simulator (Modelsim) with our standard cell library to design and simulate the organic microprocessor. The ratio between drive and load transistor for the logic gates in the library was a 1:1 ratio beneficial for area, with a minimal of 140/5 m/ m.
Figs. 3 and 11 show photographs of some microprocessors on foil. The 25-m-thick foil is highly flexible. Furthermore, the complete circuit is nearly transparent, as only the metal electrodes of gates, sources, drains and interconnect lines are reflective.
III. ARCHITECTURE AND MEASUREMENT RESULTS OF THE
Characteristic to a microprocessor is that its hardware is not dedicated to a single function or operation, but is designed such that the operations performed on (digital) inputs can be programmed and defined after manufacture of the processor. The challenge, therefore, is to manage the plurality of possible critical data paths in the microprocessor, for all different instruction codes and inevitable variations due to nature of organic technology on foil. Our microprocessor has been constructed around an 8-bit arithmetic and logic unit (ALU) which comprises three blocks as schematically represented in Fig. 4. The first block adds or subtracts the incoming numbers (arithmetic unit), the second block performs logic operations on the incoming data (logic unit) and the third block shifts the incoming bits (bit shift unit). The arithmetic unit is designed as a ripple carry adder/subtractor. Detailed control over each of these three blocks and the actual selection of the output of the ALU unit is determined by the microprocessor’s instruction set, also called
Fig. 4. Symbol (top-left), instruction set (bottom-left), and architecture (right) of the main building block of the microprocessor, namely the 8-bit ALU. Three operational code bits, opcode(2:0), are used to select among the different instructions.
operational codes or “opcodes” (Fig. 4). As the architecture depicts, the ALU executes every clock cycle instructions on each of the three units in parallel. Subsequently, a multiplexer selects the desired instruction to be executed in that clock cycle.
Fig. 5 outlines the complete architecture of the microprocessor foil. Around this ALU, a minimal set of 8-bit registers has been placed, for storing the working data (accumulator A, working registers (C0, C1 and C2) and an output register). The storing and loading of the data in these registers is also controlled by the instruction set. The registers select bits (RR in the table of Fig. 5) correspond to bits 7 and 8 of the opcode and are used to select between the four working registers, C0 to C3. Working register C3 is implemented as a hard-coded decimal 1 in order to ease the implementation of the increment and decrement instructions.
Fig. 5. (A) Architecture of the microprocessor core, comprising the Arithmetic and Logical Unit (ALU), accumulator register “A” and output register “OUT” at the top and the input multiplexer and storage registers “C” at the bottom. (B) Implemented instruction set: RR refers to the binary representation of the selected
We have tested all of the individual instructions of the microprocessor foil extensively for different bias conditions. Fig. 6(A) shows that the microprocessor can operate at up to 40 OPS, when powered at a 20-V supply voltage and an appropriate back-gate voltage. This maximum frequency is determined by the 25-ms critical path delay in the design. Fig. 6(B) shows that the microprocessor can operate at voltages down to 10 V. The critical path is defined by the subtract operation, where the carry bits need to ripple subsequently through each of the bits. As shown in Fig. 7, the contribution of these logic gates was measured separately on different kinds of ring oscillators, as a function of the capacitive load of the gates. An inverter driving a single subsequent stage has a minimum capacitive load, and in that case its gate delay is 83 s. Similarly, the minimum gate delay of a two-input NAND is 126 s, while one input is connected to . However, when a logic gate has to drive multiple subsequent stages in parallel, it is slowed down: we show in Fig. 7 that a gate driving nine identical inverter gates in parallel is slowed down to 1 ms. This gate delay, combined with the length of the critical path, explains why with our current design and topology, the processor frequency is 40 OPS. Moreover, because it was the first time a circuit of this complexity was realized in organic technology, we preferred conservative design choices. For instance, we utilized only gates with a fan-in of 2 and our signal buffering strategy was very conservative. By alleviating these restrictions and by optimizing the design, we estimate that the frequency can improve towards the hundreds of OPS range. Another reason for the current limitation to the tens of OPS range is related to the choice of logic family, where we have chosen for robustness. Other unipolar logic types (dual-gate, diode-connected) are more advantageous in terms of speed . As Figs. 6(A) and 7 also depict, the frequency of the ALU and the ring oscillator decreases when the back-gate voltage
gate delay of the individual inverters of the chain. The stage delay of inverters driving five and nine gates have corresponding labels. The triangles show the measured stage delay of two-input NAND gates driving one, five, and nine subsequent gates.
of the drive transistors increases. This can be explained by a negative -shift of the drive TFT yielding less drive current
Fig. 8. Demonstration of user-programmability of the microprocessor. (A) Time evolution of the 4-bit input signals and the 8-bit output signal when the multiplier instruction set (see Fig. 9) is implemented in the organic microprocessor foil. The top axis shows the cycle number of the program loop. (B) The 6-bit input signal (left axis) and the 7-bit output signal (right axis, which has one significant binary digit more than the input) when the running averager program (see Fig. 10) is executed. The top axis shows the cycle number of the program loop.
Fig. 9. Architecture and operation of instruction sequence generating circuits on foil. (A) Schematic of instruction generating foils: n is 5 in case of the multiplier foil and 4 for the running averager. (B) Program listing of the dedicated instruction set of the multiplier, the execution of which can be followed by the example shown in (C): the instruction lines of the code (B) have been colored using the same color code as the outcome that they produce in the multiplication of 1010 (10)
and 0111 (7) in (C). (D) shows the program instruction for the moving averager.
Furthermore, we show that our microprocessor is truly a general-purpose machine that can be programmed for multiple uses by executing instruction codes for different applications. To this end, a test board was developed that programs the microprocessor. In a first example, shown in Fig. 8(A), the microprocessor is programmed to execute a multiplication of two numbers. The solid line shows a sequence of cycles, in each of which two 4-bit numbers are multiplied to give an 8-bit output value, shown as dotted line. The input values are shown on the left scale (from 0 to 15), while the output is shown on the right scale (0 to 255). The first cycle shows the multiplication of the binary numbers 0111 (decimal 7) and 1010 (decimal 10) to 01000110 (decimal 70). This value remains at the output while two new numbers are fed in at the input (0000 and 1111) and multiplied. In the third cycle, the output of this multiplication (00000000) appears at the output while a new set is provided and executed, and so on. The processor clock can be verified to run at 40 Hz during this execution, as explained above.
Fig. 10. Demonstration of operation of the plastic microprocessor commanded by an instruction foil. (A) Decimal representation of the measured seven least significant bits of the instruction generated by the running averager instruction foil running at 70 Hz. The clock is shown at the right-hand axis. The data is valid on the rising edge of the clock. (B) Measured output of the microprocessor foil connected to the running averager instruction foil. As the input bit stream switches from 000000 to 000111, the output gradually increases to the same level over three loop cycles, but with seven significant binary digits.
In a different example, chosen from the application domain of digital signal processing, the microprocessor executes the weighed time-averaging of a stream of incoming digital inputs to reduce random noise. This algorithm is known to clean up the output signal of a sensor after digitization by an analog-to-digital converter (ADC). By virtue of its applicability to large area
Fig. 11. Photograph of the 8-bit ALU-foil.
substrates, plastic electronics is suited to develop large-area sensors , and the first plastic ADC converters were shown recently , . We implemented the algorithm of a moving averager, i.e., an averaging algorithm in which the weight of the past data decreases exponentially, and demonstrate the execution of the algorithm in Fig. 8(B). The 6-bit input provided to the microprocessor is shown as the red line: 001111 (15) during the first four loop cycles, then 111101 (61) during the next 10 cycles, then 000110 (6). The running averager calculates the weighed average as a 7-bit number, which can be seen to tend to the steady input values after they have been provided for some cycles. Here again, the clock speed of the processor is 40 Hz.
IV. INTEGRATED ORGANIC MICROPROCESSOR ON FOIL
Until now, only the ALU-foil of the microprocessor core was discussed. In the above demonstrations, the instructions for the microprocessor were generated by external test equipment. To come to a complete plastic solution, we also designed a plastic control unit, shown Fig. 9(A). This control unit has as task to take instructions from a memory in the appropriate order controlled by a program counter. These instructions are sent as opcodes to the microprocessor core. Opcodes for the program counter are also generated to enable branching in the program. In the ideal case, the program would be stored in programmable, nonvolatile memory on the foil. However, programmable nonvolatile memory compatible with plastic thin-film transistors on foil is still subject of research today and is as such not available for our experiments. Therefore, like in the early days of silicon technology, we used true read-only memory (ROM): the
SPECIFICATIONS OF THE CIRCUIT FOILS
TABLE II COMPARISON WITH THE EARLY SILICON PROCESSOR
instructions are hardcoded on the foil. A different foil is designed for every program. For the low-cost, low-complexity but high-volume applications that are envisaged here, this procedure could even be a realistic commercial scenario. The instruction sets generated by the multiplier instruction foil and the moving averager foil are shown in Fig. 9(B) and (D), respectively.
The operation of the running averager instruction foil by itself is shown in Fig. 10(A). This circuit does not contain a ripple carry adder, and therefore it has a shorter critical path compared with the microprocessor. Stand-alone, the instruction circuit can run at a clock speed of 70 Hz.
Finally,wedemonstrate thecombined operation of aninstruction foil with the microprocessor. We conducted this experiment with the running averager. The correct operation of this combination is shown in Fig. 10(B). This demonstration shows that the microprocessor can indeed accept its instruction set from a dedicated plastic circuit and is not limited to instruction sets from a test board.
In Table I, we summarize the circuits fabricated and demonstrated in plastic technology. With less than 100 W, the power consumption of the flexible chips is already quite low and could further be reduced by voltage scaling in the future , . Such very low power consumption is very important for widespread mobile applications on everyday objects.
To conclude, we compare in Table II the characteristics of the first plastic microprocessor with the early silicon processors made in p-type-only silicon technology some four decades ago. Significant correspondence can be seen regarding parameters such as gate length, supply voltage and transistor count, but some marked differences are also clear. The instruction rate of the plastic technology is about three orders of magnitude slower than the early silicon processor, as a direct consequence of the three-orders-of-magnitude lower carrier mobility in organic semiconductors. However, on the positive side, the power consumption is also four orders of magnitude smaller. In future implementations, semiconductors such as amorphous oxides  could boost the performance to an intermediate speed, with still very attractive power consumption for low-cost, lowperformance, and mobile applications.
This work was performed in a collaboration between imec and TNO in the frame of the HOLST Centre.
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Kris Myny (S’08) was born in Hasselt, Belgium, on July 26, 1980. He received the M.S. degree from the Katholieke Hogeschool Limburg, Diepenbeek, Belgium in, 2002. He is currently working toward the Ph.D. degree on the design of organic circuits at Katholieke Universiteit Leuven, Leuven, Belgium. He joined imec, Leuven, Belegium, in 2004 as a Member of the Polymer and Molecular Electronics group. His main research interests are the design, fabrication and optimization of digital organic circuits for amongst others organic RFID tags and AMOLED-backplanes.
Mr. Myny was the recipient of the imec 2010 Scientific Excellence Award.
Erik van Veenendaal received the Ph.D. degree in physical chemistry from the University of Nijmegen, Nijmegen, The Netherlands, in 2001.
In the same year, he joined Philips Research Eindhoven, Eindhoven, The Netherlands,to work on characterization and modeling of organic electronics. In 2003, with the launch of Polymer Vision as an internal Philips company, his work focused on the characterization of organic electronics enabled displays and setting up the quality and reliability program for rollable displays. Currently, his main responsibilities
as principal scientist at Polymer Vision BV, Eindhoven, include R&D into future generations of rollable displays and management of subsidy R&D programs.
Gerwin H. Gelinck received the Ph.D. degree from the Technical University of Delft, Delft, The Netherlands, in 1998.
That same year, he joined Philips Research as a Senior Scientist, where he began working on polymer and organic transistors and their use in integrated circuits, displays and memories. In 2002 he was co-founder of Polymer Vision BV, Eindhoven, The Netherlands. From 2002 to 2006, he was Chief Scientist of Polymer Vision. Since 2007 he is
Program Manager of “Organic and Oxide Circuitry”
at the Holst Centre, which is a joint research initiative of TNO and imec.
Jan Genoe (S’87–M’02) was born in Leuven, Belgium, on May 19, 1965. He received the M.S. degree in electrical engineering and Ph.D. degree from the Katholieke Universiteit Leuven, in 1988 and 1994, respectively.
Afterward, he joined the Grenoble High Magnetic Field Laboratory as a Human Capital and Mobility Fellow of the European Community. In 1997, he became a Lecturer with the Katholieke Hogeschool Limburg (KHLim), Diepenbeek, Belgium. Since
2003, he has been both Professor with KHLim and
head of the Polymer and Molecular Electronics (PME) group of imec. His current research interests are organic and oxide transistors and circuits as well as organic photovoltaics. He is the author and coauthor of approximately 90 papers in refereed journals.
Wim Dehaene (S’89–M’97–SM’04) was born in Nijmegen, The Netherlands, in 1967. He received the M.Sc. degree in electrical and mechanical engineering and Ph.D. degree from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1991 and 1996, respectively. His dissertation is entitled “CMOS integrated circuits for analog signal processing in hard disk systems.”
After receiving the M.Sc. degree, he was a Research Assistant with the ESAT-MICAS Laboratory of the Katholieke Universiteit Leuven. His research
involved the design of novel CMOS building blocks for hard disk systems. The research was first sponsored by the IWONL (Belgian Institute for Science and Research in Industry and agriculture) and later by the IWT (the Flemish institute for Scientific Research in the Industry). In November 1996, he joined Alcatel Microelectronics, Belgium. There he was a Senior Project Leader for the feasibility, design, and development of mixed-mode systems-on-chip. The application domains were telephony, xDSL and high speed wireless LAN. In July 2002, he joined the staff of the ESAT-MICAS laboratory of the Katholieke Universiteit Leuven, where he is now a Full Professor. His research domain is circuit level design of digital circuits. The current focus is on ultra low power signal processing and memories in advanced CMOS technologies. Part of this research is performed in cooperation with imec, Leuven, Belgium, where he is also a part-time Principal Scientist. He is currently teaching several classes on electrical engineering and digital circuit and system design.
Paul Heremans received the Ph.D. degree in electrical engineering from the University of Leuven, Leuven, Belgium, in 1990, on hot-carrier degradation of MOS transistors.
He then joined the Opto-electronics Group of imec, Leuven, Belgium, where he worked on optical interchip interconnects, and on high-efficiency III-V thin-film surface-textured light-emitting diodes. His current research interest is oxide and organic electronics, including circuits, backplanes and memories, as well as organic photovoltaics. He is an imec Fellow, Director of imec’s Large Area Electronics department and part-time Professor at the Electrical Engineering Department of the University of Leuven and editor of Organic Electronics.
 Historic data are collected on the Intel Museum. [Online]. Available: http://www.intel.com/about/companyinfo/museum/exhibits/4004/index.htm. The specifications can be found at http://datasheets.chipdb.org/Intel/MCS-4/ datashts/intel-4004.pdf